文件名称:Ethernet_verilog_ip_core
- 所属分类：
- VHDL编程
- 资源属性：
- [PDF]
- 上传时间：
- 2012-11-26
- 文件大小：
- 882kb
- 下载次数：
- 0次
- 提 供 者：
- houlo******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
Ethernet(以太网)verilog ip core用verilogHDL语言写的以太网软核，对学习verilog语言和以太网有很大帮助。-Ethernet (Ethernet) verilog ip core language used verilogHDL Ethernet soft-core, learning Verilog language and Ethernet are very helpful.
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ethernet
........\bench
........\.....\CVS
........\.....\...\Entries
........\.....\...\Entries.Log
........\.....\...\Repository
........\.....\...\Root
........\.....\...\Template
........\.....\verilog
........\.....\.......\CVS
........\.....\.......\...\Entries
........\.....\.......\...\Repository
........\.....\.......\...\Root
........\.....\.......\...\Template
........\.....\.......\eth_host.v
........\.....\.......\eth_memory.v
........\.....\.......\eth_phy.v
........\.....\.......\eth_phy_defines.v
........\.....\.......\tb_cop.v
........\.....\.......\tb_ethernet.v
........\.....\.......\tb_ethernet_with_cop.v
........\.....\.......\tb_eth_defines.v
........\.....\.......\tb_eth_top.v
........\.....\.......\wb_bus_mon.v
........\.....\.......\wb_master32.v
........\.....\.......\wb_master_behavioral.v
........\.....\.......\wb_model_defines.v
........\.....\.......\wb_slave_behavioral.v
........\CVS
........\...\Entries
........\...\Entries.Log
........\...\Repository
........\...\Root
........\...\Template
........\doc
........\...\CVS
........\...\...\Entries
........\...\...\Entries.Log
........\...\...\Repository
........\...\...\Root
........\...\...\Template
........\...\ethernet_datasheet_OC_head.pdf
........\...\ethernet_product_brief_OC_head.pdf
........\...\eth_design_document.pdf
........\...\eth_speci.pdf
........\...\src
........\...\...\CVS
........\...\...\...\Entries
........\...\...\...\Repository
........\...\...\...\Root
........\...\...\...\Template
........\...\...\ethernet_datasheet_OC_head.doc
........\...\...\ethernet_product_brief_OC_head.doc
........\...\...\eth_design_document.doc
........\...\...\eth_speci.doc
........\README.txt
........\rtl
........\...\CVS
........\...\...\Entries
........\...\...\Entries.Log
........\...\...\Repository
........\...\...\Root
........\...\...\Template
........\...\verilog
........\...\.......\BUGS
........\...\.......\CVS
........\...\.......\...\Entries
........\...\.......\...\Repository
........\...\.......\...\Root
........\...\.......\...\Template
........\...\.......\eth_clockgen.v
........\...\.......\eth_cop.v
........\...\.......\eth_crc.v
........\...\.......\eth_defines.v
........\...\.......\eth_fifo.v
........\...\.......\eth_maccontrol.v
........\...\.......\eth_macstatus.v
........\...\.......\eth_miim.v
........\...\.......\eth_outputcontrol.v
........\...\.......\eth_random.v
........\...\.......\eth_receivecontrol.v
........\...\.......\eth_register.v
........\...\.......\eth_registers.v
........\...\.......\eth_rxaddrcheck.v
........\...\.......\eth_rxcounters.v
........\...\.......\eth_rxethmac.v
........\...\.......\eth_rxstatem.v
........\...\.......\eth_shiftreg.v
........\...\.......\eth_spram_256x32.v
........\...\.......\eth_top.v
........\...\.......\eth_transmitcontrol.v
........\...\.......\eth_txcounters.v
........\...\.......\eth_txethmac.v
........\...\.......\eth_txstatem.v
........\...\.......\eth_wishbone.v
........\...\.......\timescale.v
........\...\.......\TODO
........\...\.......\xilinx_dist_ram_16x32.v
........\sim
........\...\CVS
........\bench
........\.....\CVS
........\.....\...\Entries
........\.....\...\Entries.Log
........\.....\...\Repository
........\.....\...\Root
........\.....\...\Template
........\.....\verilog
........\.....\.......\CVS
........\.....\.......\...\Entries
........\.....\.......\...\Repository
........\.....\.......\...\Root
........\.....\.......\...\Template
........\.....\.......\eth_host.v
........\.....\.......\eth_memory.v
........\.....\.......\eth_phy.v
........\.....\.......\eth_phy_defines.v
........\.....\.......\tb_cop.v
........\.....\.......\tb_ethernet.v
........\.....\.......\tb_ethernet_with_cop.v
........\.....\.......\tb_eth_defines.v
........\.....\.......\tb_eth_top.v
........\.....\.......\wb_bus_mon.v
........\.....\.......\wb_master32.v
........\.....\.......\wb_master_behavioral.v
........\.....\.......\wb_model_defines.v
........\.....\.......\wb_slave_behavioral.v
........\CVS
........\...\Entries
........\...\Entries.Log
........\...\Repository
........\...\Root
........\...\Template
........\doc
........\...\CVS
........\...\...\Entries
........\...\...\Entries.Log
........\...\...\Repository
........\...\...\Root
........\...\...\Template
........\...\ethernet_datasheet_OC_head.pdf
........\...\ethernet_product_brief_OC_head.pdf
........\...\eth_design_document.pdf
........\...\eth_speci.pdf
........\...\src
........\...\...\CVS
........\...\...\...\Entries
........\...\...\...\Repository
........\...\...\...\Root
........\...\...\...\Template
........\...\...\ethernet_datasheet_OC_head.doc
........\...\...\ethernet_product_brief_OC_head.doc
........\...\...\eth_design_document.doc
........\...\...\eth_speci.doc
........\README.txt
........\rtl
........\...\CVS
........\...\...\Entries
........\...\...\Entries.Log
........\...\...\Repository
........\...\...\Root
........\...\...\Template
........\...\verilog
........\...\.......\BUGS
........\...\.......\CVS
........\...\.......\...\Entries
........\...\.......\...\Repository
........\...\.......\...\Root
........\...\.......\...\Template
........\...\.......\eth_clockgen.v
........\...\.......\eth_cop.v
........\...\.......\eth_crc.v
........\...\.......\eth_defines.v
........\...\.......\eth_fifo.v
........\...\.......\eth_maccontrol.v
........\...\.......\eth_macstatus.v
........\...\.......\eth_miim.v
........\...\.......\eth_outputcontrol.v
........\...\.......\eth_random.v
........\...\.......\eth_receivecontrol.v
........\...\.......\eth_register.v
........\...\.......\eth_registers.v
........\...\.......\eth_rxaddrcheck.v
........\...\.......\eth_rxcounters.v
........\...\.......\eth_rxethmac.v
........\...\.......\eth_rxstatem.v
........\...\.......\eth_shiftreg.v
........\...\.......\eth_spram_256x32.v
........\...\.......\eth_top.v
........\...\.......\eth_transmitcontrol.v
........\...\.......\eth_txcounters.v
........\...\.......\eth_txethmac.v
........\...\.......\eth_txstatem.v
........\...\.......\eth_wishbone.v
........\...\.......\timescale.v
........\...\.......\TODO
........\...\.......\xilinx_dist_ram_16x32.v
........\sim
........\...\CVS