文件名称:vhdlsource
介绍说明－－下载内容均来自于网络，请自行研究使用
用verilog hdl编写的一些例程，包括加法器/减法器等等，例子较多就不一一列举了-Verilog hdl prepared with some routines, including the adder/subtraction, etc., for example, more is not to enumerate the
(系统自动生成,下载前可以参看下载内容)
下载文件列表
vhdlsource
..........\add4_1.v
..........\add4_2.v
..........\add4_3.v
..........\count4.v
..........\full_add1.v
..........\full_add2.v
..........\full_add3.v
..........\full_add4.v
..........\full_add5.v
..........\half_add1.v
..........\half_add2.v
..........\half_add3.v
..........\half_add4.v
..........\mux2_1a.v
..........\mux2_1b.v
..........\mux2_1c.v
..........\mux4_1a.v
..........\mux4_1b.v
..........\mux4_1c.v
..........\mux4_1d.v
..........\add4_1.v
..........\add4_2.v
..........\add4_3.v
..........\count4.v
..........\full_add1.v
..........\full_add2.v
..........\full_add3.v
..........\full_add4.v
..........\full_add5.v
..........\half_add1.v
..........\half_add2.v
..........\half_add3.v
..........\half_add4.v
..........\mux2_1a.v
..........\mux2_1b.v
..........\mux2_1c.v
..........\mux4_1a.v
..........\mux4_1b.v
..........\mux4_1c.v
..........\mux4_1d.v