文件名称:VerilogHDL_advanced_digital_design_code_Ch9

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VerilogHDL_advanced_digital_design_code_Ch9

VerilogHDL高级数字设计源码Ch9-Advanced digital design VerilogHDL_advanced_digital_design_code_Ch9VerilogHDL source Ch9
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Chapter 9

.........\ADDVB_Models_9.doc

.........\add_16_pipe.v

.........\Bubble Sorter

.........\.............\Bubble_sort.v

.........\.............\t_Bubble_Sort.v

.........\.............\_vti_cnf

.........\.............\........\Bubble_sort.v

.........\DSP

.........\...\decimator_1.v

.........\...\decimator_2.v

.........\...\decimator_3.v

.........\...\FIR_Gaussian.v

.........\...\IIR_Filter.v

.........\...\integrator_par.v

.........\...\Integrator_Seq.v

.........\...\test_FIR_Gaussian.v

.........\...\test_IIR.v

.........\...\t_decimator_1.v

.........\...\t_decimator_2.v

.........\...\t_decimator_3.v

.........\...\t_integrator_par.v

.........\...\t_Integrator_Seq.v

.........\...\_vti_cnf

.........\...\........\decimator_1.v

.........\...\........\decimator_2.v

.........\...\........\decimator_3.v

.........\...\........\FIR_Gaussian.v

.........\...\........\IIR_Filter.v

.........\...\........\integrator_par.v

.........\...\........\Integrator_Seq.v

.........\...\........\test_FIR_Gaussian.v

.........\...\........\test_IIR.v

.........\...\........\t_decimator_1.v

.........\...\........\t_decimator_2.v

.........\...\........\t_decimator_3.v

.........\...\........\t_integrator_par.v

.........\...\........\t_Integrator_Seq.v

.........\Pipeline and FIFO

.........\.................\Circular_Buffer_1.v

.........\.................\Circular_Buffer_2.v

.........\.................\FIFO_Buffer.v

.........\.................\Ser_Par_Conv_32.v

.........\.................\Ser_Par_Conv_8.v

.........\.................\t_Circular_Buffers.v

.........\.................\t_FIFO_Buffer.v

.........\.................\t_FIFO_Clock_Domain_Synch.v

.........\.................\t_Ser_Par_Conv_32.v

.........\.................\t_Ser_Par_Conv_8.v

.........\.................\t_write_synch.v

.........\.................\write_synch.v

.........\.................\_vti_cnf

.........\.................\........\Circular_Buffer_1.v

.........\.................\........\Circular_Buffer_2.v

.........\.................\........\FIFO_Buffer.v

.........\.................\........\Ser_Par_Conv_32.v

.........\.................\........\Ser_Par_Conv_8.v

.........\.................\........\t_Circular_Buffers.v

.........\.................\........\t_FIFO_Buffer.v

.........\.................\........\t_FIFO_Clock_Domain_Synch.v

.........\.................\........\t_Ser_Par_Conv_32.v

.........\.................\........\t_Ser_Par_Conv_8.v

.........\.................\........\t_write_synch.v

.........\.................\........\write_synch.v

.........\Pixel Converter

.........\...............\Image_Converter_0.v

.........\...............\Image_Converter_1.v

.........\...............\Image_converter_2.v

.........\...............\Image_Converter_Baseline.v

.........\...............\t_Image_Converter_0.v

.........\...............\t_Image_Converter_1.v

.........\...............\t_Image_Converter_2.v

.........\...............\t_Image_Converter_Baseline.v

.........\...............\_vti_cnf

.........\...............\........\Image_Converter_0.v

.........\...............\........\Image_Converter_1.v

.........\...............\........\Image_converter_2.v

.........\...............\........\Image_Converter_Baseline.v

.........\...............\........\t_Image_Converter_0.v

.........\...............\........\t_Image_Converter_1.v

.........\...............\........\t_Image_Converter_2.v

.........\...............\........\t_Image_Converter_Baseline.v

.........\_vti_cnf

.........\........\ADDVB_Models_9.doc

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