文件名称:VerilogHDL_advanced_digital_design_code_Ch9
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VerilogHDL_advanced_digital_design_code_Ch9
VerilogHDL高级数字设计源码Ch9
VerilogHDL高级数字设计源码Ch9
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压缩包 : 87361051veriloghdl_advanced_digital_design_code_ch9.rar 列表 Chapter 9\ADDVB_Models_9.doc Chapter 9\add_16_pipe.v Chapter 9\Bubble Sorter\Bubble_sort.v Chapter 9\Bubble Sorter\t_Bubble_Sort.v Chapter 9\Bubble Sorter\_vti_cnf\Bubble_sort.v Chapter 9\Bubble Sorter\_vti_cnf Chapter 9\Bubble Sorter Chapter 9\DSP\decimator_1.v Chapter 9\DSP\decimator_2.v Chapter 9\DSP\decimator_3.v Chapter 9\DSP\FIR_Gaussian.v Chapter 9\DSP\IIR_Filter.v Chapter 9\DSP\integrator_par.v Chapter 9\DSP\Integrator_Seq.v Chapter 9\DSP\test_FIR_Gaussian.v Chapter 9\DSP\test_IIR.v Chapter 9\DSP\t_decimator_1.v Chapter 9\DSP\t_decimator_2.v Chapter 9\DSP\t_decimator_3.v Chapter 9\DSP\t_integrator_par.v Chapter 9\DSP\t_Integrator_Seq.v Chapter 9\DSP\_vti_cnf\decimator_1.v Chapter 9\DSP\_vti_cnf\decimator_2.v Chapter 9\DSP\_vti_cnf\decimator_3.v Chapter 9\DSP\_vti_cnf\FIR_Gaussian.v Chapter 9\DSP\_vti_cnf\IIR_Filter.v Chapter 9\DSP\_vti_cnf\integrator_par.v Chapter 9\DSP\_vti_cnf\Integrator_Seq.v Chapter 9\DSP\_vti_cnf\test_FIR_Gaussian.v Chapter 9\DSP\_vti_cnf\test_IIR.v Chapter 9\DSP\_vti_cnf\t_decimator_1.v Chapter 9\DSP\_vti_cnf\t_decimator_2.v Chapter 9\DSP\_vti_cnf\t_decimator_3.v Chapter 9\DSP\_vti_cnf\t_integrator_par.v Chapter 9\DSP\_vti_cnf\t_Integrator_Seq.v Chapter 9\DSP\_vti_cnf Chapter 9\DSP Chapter 9\Pipeline and FIFO\Circular_Buffer_1.v Chapter 9\Pipeline and FIFO\Circular_Buffer_2.v Chapter 9\Pipeline and FIFO\FIFO_Buffer.v Chapter 9\Pipeline and FIFO\Ser_Par_Conv_32.v Chapter 9\Pipeline and FIFO\Ser_Par_Conv_8.v Chapter 9\Pipeline and FIFO\t_Circular_Buffers.v Chapter 9\Pipeline and FIFO\t_FIFO_Buffer.v Chapter 9\Pipeline and FIFO\t_FIFO_Clock_Domain_Synch.v Chapter 9\Pipeline and FIFO\t_Ser_Par_Conv_32.v Chapter 9\Pipeline and FIFO\t_Ser_Par_Conv_8.v Chapter 9\Pipeline and FIFO\t_write_synch.v Chapter 9\Pipeline and FIFO\write_synch.v Chapter 9\Pipeline and FIFO\_vti_cnf\Circular_Buffer_1.v Chapter 9\Pipeline and FIFO\_vti_cnf\Circular_Buffer_2.v Chapter 9\Pipeline and FIFO\_vti_cnf\FIFO_Buffer.v Chapter 9\Pipeline and FIFO\_vti_cnf\Ser_Par_Conv_32.v Chapter 9\Pipeline and FIFO\_vti_cnf\Ser_Par_Conv_8.v Chapter 9\Pipeline and FIFO\_vti_cnf\t_Circular_Buffers.v Chapter 9\Pipeline and FIFO\_vti_cnf\t_FIFO_Buffer.v Chapter 9\Pipeline and FIFO\_vti_cnf\t_FIFO_Clock_Domain_Synch.v Chapter 9\Pipeline and FIFO\_vti_cnf\t_Ser_Par_Conv_32.v Chapter 9\Pipeline and FIFO\_vti_cnf\t_Ser_Par_Conv_8.v Chapter 9\Pipeline and FIFO\_vti_cnf\t_write_synch.v Chapter 9\Pipeline and FIFO\_vti_cnf\write_synch.v Chapter 9\Pipeline and FIFO\_vti_cnf Chapter 9\Pipeline and FIFO Chapter 9\Pixel Converter\Image_Converter_0.v Chapter 9\Pixel Converter\Image_Converter_1.v Chapter 9\Pixel Converter\Image_converter_2.v Chapter 9\Pixel Converter\Image_Converter_Baseline.v Chapter 9\Pixel Converter\t_Image_Converter_0.v Chapter 9\Pixel Converter\t_Image_Converter_1.v Chapter 9\Pixel Converter\t_Image_Converter_2.v Chapter 9\Pixel Converter\t_Image_Converter_Baseline.v Chapter 9\Pixel Converter\_vti_cnf\Image_Converter_0.v Chapter 9\Pixel Converter\_vti_cnf\Image_Converter_1.v Chapter 9\Pixel Converter\_vti_cnf\Image_converter_2.v Chapter 9\Pixel Converter\_vti_cnf\Image_Converter_Baseline.v Chapter 9\Pixel Converter\_vti_cnf\t_Image_Converter_0.v Chapter 9\Pixel Converter\_vti_cnf\t_Image_Converter_1.v Chapter 9\Pixel Converter\_vti_cnf\t_Image_Converter_2.v Chapter 9\Pixel Converter\_vti_cnf\t_Image_Converter_Baseline.v Chapter 9\Pixel Converter\_vti_cnf Chapter 9\Pixel Converter Chapter 9\_vti_cnf\ADDVB_Models_9.doc Chapter 9\_vti_cnf Chapter 9