VerilogHDL_advanced_digital_design_code_Ch6

...........................................\ADDVB_Models_6.doc

...........................................\Add_Accum_1.v

...........................................\Add_Accum_2.v

...........................................\Add_Accum_both.v

...........................................\alu_with_z1.v

...........................................\badd_4.v

...........................................\BCD_to_Excess_3a.v

...........................................\BCD_to_Excess_3b.v

...........................................\BCD_to_Excess_3b_Post.v

...........................................\BCD_to_Excess_3c.v

...........................................\BCD_to_Excess_3c_Post.v

...........................................\Bi_dir_bus.v

...........................................\boole_opt.v

...........................................\count_ones_a.v

...........................................\count_ones_b.v

...........................................\count_ones_b0.v

...........................................\count_ones_b1.v

...........................................\count_ones_b2.v

...........................................\count_ones_c.v

...........................................\count_ones_d.v

...........................................\count_ones_IMP.v

...........................................\count_ones_SD.v

...........................................\count_ones_SD_0.v

...........................................\count_ones_SM.v

...........................................\D_reg4_a.v

...........................................\expression_sub.v

...........................................\expression_sub_nb.v

...........................................\for_and_loop_comb.v

...........................................\Latched_Seven_Seg_Display.v

...........................................\latch_if1.v

...........................................\latch_if2.v

...........................................\multiple_reg_assign.v

...........................................\mux_4pri.v

...........................................\mux_latch.v

...........................................\mux_logic.v

...........................................\mux_reg.v

...........................................\NRZI.v

...........................................\NRZ_2_Manchester_Mealy.v

...........................................\NRZ_2_Manchester_Mealy_Post.v

...........................................\NRZ_2_Manchester_Moore.v

...........................................\NRZ_2_Manchester_Moore_Post.v

...........................................\operator_group.v

...........................................\or4_behav.v

...........................................\or4_behav_latch.v

...........................................\or_nand.v

...........................................\res_share.v

...........................................\ripple_counter.v

...........................................\Seq_Rec_3_1s.v

...........................................\Seq_Rec_3_1s_Mealy.v

...........................................\Seq_Rec_3_1s_Moore.v

...........................................\Seq_Rec_3_1s_Shft_Reg.v

...........................................\Seq_Rec_Moore_imp.v

...........................................\shifter_1.v

...........................................\shifter_2.v

...........................................\swap_synch.v

...........................................\Test_count_ones_a.v

...........................................\Test_count_ones_b.v

...........................................\Test_count_ones_c.v

...........................................\Test_count_ones_d.v

...........................................\Test_count_ones_IMP.v

...........................................\Test_count_ones_SD.v

...........................................\Test_count_ones_SD_0.v

...........................................\Test_count_ones_SM.v

...........................................\test_NRZ_2_Manchester_Moore.v

...........................................\Test_Seq_Rec_Moore_imp.v

...........................................\t_BCD_