文件名称:VerilogHDL_advanced_digital_design_code_Ch4
- 所属分类：
- VHDL编程
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- [WORD]
- 上传时间：
- 2012-11-26
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- 21kb
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- lianl******
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Verilog HDL 高级数字设计源码 _chapter4-Advanced Digital Design Verilog HDL source _chapter4
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下载文件列表
VerilogHDL_advanced_digital_design_code_Ch 4
............................................\ADDVB_Models_4.doc
............................................\Add_rca_4.v
............................................\AOI_str.v
............................................\AOI_UDP.v
............................................\compare_2_str.v
............................................\compare_4_str.v
............................................\Mux_2_32_CA.v
............................................\Mux_4_32_CA.v
............................................\Mux_4_32_case.v
............................................\Mux_4_32_CA_if.v
............................................\test_hiZ.v
............................................\t_Add_full_ASIC.v
............................................\t_Add_full_unit_delay.v
............................................\t_Add_half.v
............................................\t_Add_rca_4_Unit_Delay.v
............................................\_vti_cnf
............................................\........\ADDVB_Models_4.doc
............................................\........\Add_rca_4.v
............................................\........\AOI_str.v
............................................\........\AOI_UDP.v
............................................\........\compare_2_str.v
............................................\........\compare_4_str.v
............................................\........\Mux_2_32_CA.v
............................................\........\Mux_4_32_CA.v
............................................\........\Mux_4_32_case.v
............................................\........\Mux_4_32_CA_if.v
............................................\........\test_hiZ.v
............................................\........\t_Add_full_ASIC.v
............................................\........\t_Add_full_unit_delay.v
............................................\........\t_Add_half.v
............................................\........\t_Add_rca_4_Unit_Delay.v
............................................\ADDVB_Models_4.doc
............................................\Add_rca_4.v
............................................\AOI_str.v
............................................\AOI_UDP.v
............................................\compare_2_str.v
............................................\compare_4_str.v
............................................\Mux_2_32_CA.v
............................................\Mux_4_32_CA.v
............................................\Mux_4_32_case.v
............................................\Mux_4_32_CA_if.v
............................................\test_hiZ.v
............................................\t_Add_full_ASIC.v
............................................\t_Add_full_unit_delay.v
............................................\t_Add_half.v
............................................\t_Add_rca_4_Unit_Delay.v
............................................\_vti_cnf
............................................\........\ADDVB_Models_4.doc
............................................\........\Add_rca_4.v
............................................\........\AOI_str.v
............................................\........\AOI_UDP.v
............................................\........\compare_2_str.v
............................................\........\compare_4_str.v
............................................\........\Mux_2_32_CA.v
............................................\........\Mux_4_32_CA.v
............................................\........\Mux_4_32_case.v
............................................\........\Mux_4_32_CA_if.v
............................................\........\test_hiZ.v
............................................\........\t_Add_full_ASIC.v
............................................\........\t_Add_full_unit_delay.v
............................................\........\t_Add_half.v
............................................\........\t_Add_rca_4_Unit_Delay.v