文件名称:RISC_Core.ZIP
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 333kb
- 下载次数：
- 0次
- 提 供 者：
- jinzh******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序-This is an 8-bit RISC CPU on the design of the article, which includes using the Verilog language CPU core procedures
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RISC
(系统自动生成,下载前可以参看下载内容)
下载文件列表
example_asm.txt
risc8.pdf
risc8_asm_pl.txt
risc8_tar.gz
verilog
.......\bin
.......\...\example.asm
.......\...\example.hex
.......\...\example.mem
.......\...\risc8_asm.pl
.......\doc
.......\...\risc8.pdf
.......\...\risc8.ps
.......\sim
.......\...\asm
.......\...\...\and.asm
.......\...\...\and.mem
.......\...\...\arith.asm
.......\...\...\arith.mem
.......\...\...\assemble_all
.......\...\...\divide.asm
.......\...\...\divide.mem
.......\...\...\flags.asm
.......\...\...\flags.mem
.......\...\...\interrupt.asm
.......\...\...\interrupt.mem
.......\...\...\jmp.asm
.......\...\...\jmp.mem
.......\...\...\loadstore.asm
.......\...\...\loadstore.mem
.......\...\...\logic.asm
.......\...\...\logic.mem
.......\...\...\moves.asm
.......\...\...\moves.mem
.......\...\...\multiply.asm
.......\...\...\multiply.mem
.......\...\...\or.asm
.......\...\...\or.mem
.......\...\...\staldapshpop.asm
.......\...\...\staldapshpop.mem
.......\...\...\waitstates.asm
.......\...\...\waitstates.mem
.......\...\compile
.......\...\DW01_add.v
.......\...\reg.mem
.......\...\regression
.......\...\risc8.cfg
.......\...\run_batch
.......\...\run_interac
.......\...\test.mem
.......\...\test.v
.......\src
.......\...\rbcla_adder.v
.......\...\risc8.v
.......\...\risc8_alu.v
.......\...\risc8_constants.v
.......\...\risc8_control.v
.......\...\risc8_parameters.v
.......\...\risc8_regb_biu.v
.......\syn
.......\...\risc8_dc_compile.scr
risc8.pdf
risc8_asm_pl.txt
risc8_tar.gz
verilog
.......\bin
.......\...\example.asm
.......\...\example.hex
.......\...\example.mem
.......\...\risc8_asm.pl
.......\doc
.......\...\risc8.pdf
.......\...\risc8.ps
.......\sim
.......\...\asm
.......\...\...\and.asm
.......\...\...\and.mem
.......\...\...\arith.asm
.......\...\...\arith.mem
.......\...\...\assemble_all
.......\...\...\divide.asm
.......\...\...\divide.mem
.......\...\...\flags.asm
.......\...\...\flags.mem
.......\...\...\interrupt.asm
.......\...\...\interrupt.mem
.......\...\...\jmp.asm
.......\...\...\jmp.mem
.......\...\...\loadstore.asm
.......\...\...\loadstore.mem
.......\...\...\logic.asm
.......\...\...\logic.mem
.......\...\...\moves.asm
.......\...\...\moves.mem
.......\...\...\multiply.asm
.......\...\...\multiply.mem
.......\...\...\or.asm
.......\...\...\or.mem
.......\...\...\staldapshpop.asm
.......\...\...\staldapshpop.mem
.......\...\...\waitstates.asm
.......\...\...\waitstates.mem
.......\...\compile
.......\...\DW01_add.v
.......\...\reg.mem
.......\...\regression
.......\...\risc8.cfg
.......\...\run_batch
.......\...\run_interac
.......\...\test.mem
.......\...\test.v
.......\src
.......\...\rbcla_adder.v
.......\...\risc8.v
.......\...\risc8_alu.v
.......\...\risc8_constants.v
.......\...\risc8_control.v
.......\...\risc8_parameters.v
.......\...\risc8_regb_biu.v
.......\syn
.......\...\risc8_dc_compile.scr