文件名称:fifo
介绍说明－－下载内容均来自于网络，请自行研究使用
使用Verilog语言编写，把FPGA配置成一个fifo-The use of Verilog language, the FPGA configuration into a fifo
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fifo与串口
..........\baud.v
..........\baud1.v
..........\data_path.v
..........\decode.v
..........\dpram16x8.v
..........\dpraml_16x8.v
..........\dpram_16x8.v
..........\fifo.v
..........\fifo_tmpl.v
..........\inter.v
..........\inter_tb.v
..........\rcvr.v
..........\rcvr_lattice.v
..........\rcvr_old.v
..........\rcvr_tb.v
..........\reg_data_out.v
..........\txmit.v
..........\txmit1.v
..........\txmit_tb.v
..........\Uart4_top.v
..........\uart4_top_tb.v
..........\UART_FIFO.v
..........\UART_FIFO_nr.v
..........\baud.v
..........\baud1.v
..........\data_path.v
..........\decode.v
..........\dpram16x8.v
..........\dpraml_16x8.v
..........\dpram_16x8.v
..........\fifo.v
..........\fifo_tmpl.v
..........\inter.v
..........\inter_tb.v
..........\rcvr.v
..........\rcvr_lattice.v
..........\rcvr_old.v
..........\rcvr_tb.v
..........\reg_data_out.v
..........\txmit.v
..........\txmit1.v
..........\txmit_tb.v
..........\Uart4_top.v
..........\uart4_top_tb.v
..........\UART_FIFO.v
..........\UART_FIFO_nr.v