文件名称:clkgen
介绍说明－－下载内容均来自于网络，请自行研究使用
用ＭＡＴＬＡＢ产生各种时钟信号，对于不同的模块产生适当的始终信号．
相关搜索： clkgen
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clkgen
......\clkgen.cr.mti
......\clkgen.mpf
......\clk_div.v
......\clk_gen.v
......\test.v
......\top.fsdb
......\transcript
......\work
......\....\clk_div
......\....\.......\verilog.asm
......\....\.......\_primary.dat
......\....\.......\_primary.vhd
......\....\clk_gen
......\....\.......\verilog.asm
......\....\.......\_primary.dat
......\....\.......\_primary.vhd
......\....\top
......\....\...\verilog.asm
......\....\...\_primary.dat
......\....\...\_primary.vhd
......\....\_info
......\clkgen.cr.mti
......\clkgen.mpf
......\clk_div.v
......\clk_gen.v
......\test.v
......\top.fsdb
......\transcript
......\work
......\....\clk_div
......\....\.......\verilog.asm
......\....\.......\_primary.dat
......\....\.......\_primary.vhd
......\....\clk_gen
......\....\.......\verilog.asm
......\....\.......\_primary.dat
......\....\.......\_primary.vhd
......\....\top
......\....\...\verilog.asm
......\....\...\_primary.dat
......\....\...\_primary.vhd
......\....\_info