搜索资源列表
clkgen
- verilog 编写的pic16c5x时钟模块-verilog prepared pic16c5x clock module
clkgen
- 用ＭＡＴＬＡＢ产生各种时钟信号，对于不同的模块产生适当的始终信号．
clkgen
- 用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.
clk
- 时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件
clkgen
- verilog 编写的pic16c5x时钟模块-verilog prepared pic16c5x clock module
clkgen
- 用ＭＡＴＬＡＢ产生各种时钟信号，对于不同的模块产生适当的始终信号．
clkgen
- 用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.-CPLD with minimal resources, using Verilog in QuartusII7.1 to achieve the 1280 frequency.
clk
- 时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件-Clock Generator clkgen use of external clock signal clk to generate a series of clock signal clk1, fetch, alu_clk sent to other parts of the CPU
iiscode
- 用Verilog写的一个简单的IIs控制器，分为clkgen时钟分频模块和transcon传输控制模块。其中transcon模块主要部分为一个有限状态机实现的满足IIS标准的输出。 另附一个简单的Testcase以及得到的波形。-Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v
clkgen
- 移位寄存器实现分频，避免大量使用分频代码-Frequency shift registers
clk-axi-clkgen
- AXI clkgen driver for Linux.
clkgen_defs
- C-code for register scope clkgen.
extdev
- Register r bootsel, scope clkgen.
st-clkgen-pll
- Binding for a ST pll clock driver.
st-clkgen-mux
- Binding for a ST multiplexed clock driver.
st-clkgen-vcc
- Binding for a type of STMicroelectronics clock crossbar (VCC).
axi-clkgen
- This binding uses the common clock binding.
clkgen-mux
- clkgen-mux.c: ST GEN-MUX Clock driver.
clk-axi-clkgen
- AXI clkgen driver for Linux v2.13.6.
st-clkgen
- Linux MegaRAID driver for SAS based RAID controllers.