文件名称:CLOCK_co-design_of_C_and_Verilog
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A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
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下载文件列表
CLOCK
.....\homework3.v
.....\hw3
.....\...\HW3.doc
.....\...\output_use_de.c
.....\HW3.doc
.....\hw3testbench.v
.....\output_use_de.c
.....\homework3.v
.....\hw3
.....\...\HW3.doc
.....\...\output_use_de.c
.....\HW3.doc
.....\hw3testbench.v
.....\output_use_de.c