文件名称:PD_using_FPGA

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 436kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 宇*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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verilog编写基于fpga的鉴相器模块-Verilog preparation phase of the FPGA-based module
相关搜索: 鉴相器
fpga
PD_using_FPGA

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下载文件列表

PD_using_FPGA

.............\phase_control.bdf

.............\phase_test

.............\..........\db

.............\..........\..\add_sub_nsh.tdf

.............\..........\..\cntr_2ii.tdf

.............\..........\..\phase_test.asm.qmsg

.............\..........\..\phase_test.cbx.xml

.............\..........\..\phase_test.cmp.cdb

.............\..........\..\phase_test.cmp.hdb

.............\..........\..\phase_test.cmp.kpt

.............\..........\..\phase_test.cmp.logdb

.............\..........\..\phase_test.cmp.rdb

.............\..........\..\phase_test.cmp.tdb

.............\..........\..\phase_test.cmp0.ddb

.............\..........\..\phase_test.dbp

.............\..........\..\phase_test.db_info

.............\..........\..\phase_test.eco.cdb

.............\..........\..\phase_test.eds_overflow

.............\..........\..\phase_test.fit.qmsg

.............\..........\..\phase_test.fnsim.hdb

.............\..........\..\phase_test.fnsim.qmsg

.............\..........\..\phase_test.hier_info

.............\..........\..\phase_test.hif

.............\..........\..\phase_test.map.cdb

.............\..........\..\phase_test.map.hdb

.............\..........\..\phase_test.map.logdb

.............\..........\..\phase_test.map.qmsg

.............\..........\..\phase_test.pre_map.cdb

.............\..........\..\phase_test.pre_map.hdb

.............\..........\..\phase_test.psp

.............\..........\..\phase_test.rtlv.hdb

.............\..........\..\phase_test.rtlv_sg.cdb

.............\..........\..\phase_test.rtlv_sg_swap.cdb

.............\..........\..\phase_test.sgdiff.cdb

.............\..........\..\phase_test.sgdiff.hdb

.............\..........\..\phase_test.signalprobe.cdb

.............\..........\..\phase_test.sim.hdb

.............\..........\..\phase_test.sim.qmsg

.............\..........\..\phase_test.sim.rdb

.............\..........\..\phase_test.sim.vwf

.............\..........\..\phase_test.sld_design_entry.sci

.............\..........\..\phase_test.sld_design_entry_dsc.sci

.............\..........\..\phase_test.smp_dump.txt

.............\..........\..\phase_test.syn_hier_info

.............\..........\..\phase_test.tan.qmsg

.............\..........\..\wed.zsf

.............\..........\phase_counter.bsf

.............\..........\phase_counter.inc

.............\..........\phase_counter.v

.............\..........\phase_counter_bb.v

.............\..........\phase_pll.bsf

.............\..........\phase_pll.inc

.............\..........\phase_pll.ppf

.............\..........\phase_pll.v

.............\..........\phase_pll_bb.v



.............\..........\phase_pll_waveforms.html

.............\..........\phase_test.asm.rpt

.............\..........\phase_test.bsf

.............\..........\phase_test.done

.............\..........\phase_test.fit.rpt

.............\..........\phase_test.fit.smsg

.............\..........\phase_test.fit.summary

.............\..........\phase_test.flow.rpt

.............\..........\phase_test.map.rpt

.............\..........\phase_test.map.summary

.............\..........\phase_test.pin

.............\..........\phase_test.pof

.............\..........\phase_test.qpf

.............\..........\phase_test.qsf

.............\..........\phase_test.qws

.............\..........\phase_test.sim.rpt

.............\..........\phase_test.sof

.............\..........\phase_test.tan.rpt

.............\..........\phase_test.tan.summary

.............\..........\phase_test.vwf

.............\phase_test.v

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