文件名称:PD_using_FPGA
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog编写基于fpga的鉴相器模块
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 39709582pd_using_fpga.rar 列表 PD_using_FPGA\phase_control.bdf PD_using_FPGA\phase_test.v PD_using_FPGA\phase_test\phase_counter.bsf PD_using_FPGA\phase_test\phase_counter.inc PD_using_FPGA\phase_test\phase_counter.v PD_using_FPGA\phase_test\phase_counter_bb.v PD_using_FPGA\phase_test\phase_pll.bsf PD_using_FPGA\phase_test\phase_pll.inc PD_using_FPGA\phase_test\phase_pll.ppf PD_using_FPGA\phase_test\phase_pll.v PD_using_FPGA\phase_test\phase_pll_bb.v PD_using_FPGA\phase_test\phase_pll_wave0.jpg PD_using_FPGA\phase_test\phase_pll_waveforms.html PD_using_FPGA\phase_test\phase_test.asm.rpt PD_using_FPGA\phase_test\phase_test.bsf PD_using_FPGA\phase_test\phase_test.done PD_using_FPGA\phase_test\phase_test.fit.rpt PD_using_FPGA\phase_test\phase_test.fit.smsg PD_using_FPGA\phase_test\phase_test.fit.summary PD_using_FPGA\phase_test\phase_test.flow.rpt PD_using_FPGA\phase_test\phase_test.map.rpt PD_using_FPGA\phase_test\phase_test.map.summary PD_using_FPGA\phase_test\phase_test.pin PD_using_FPGA\phase_test\phase_test.pof PD_using_FPGA\phase_test\phase_test.qpf PD_using_FPGA\phase_test\phase_test.qsf PD_using_FPGA\phase_test\phase_test.qws PD_using_FPGA\phase_test\phase_test.sim.rpt PD_using_FPGA\phase_test\phase_test.sof PD_using_FPGA\phase_test\phase_test.tan.rpt PD_using_FPGA\phase_test\phase_test.tan.summary PD_using_FPGA\phase_test\phase_test.vwf PD_using_FPGA\phase_test\db\add_sub_nsh.tdf PD_using_FPGA\phase_test\db\cntr_2ii.tdf PD_using_FPGA\phase_test\db\phase_test.(0).cnf.cdb PD_using_FPGA\phase_test\db\phase_test.(0).cnf.hdb PD_using_FPGA\phase_test\db\phase_test.(1).cnf.cdb PD_using_FPGA\phase_test\db\phase_test.(1).cnf.hdb PD_using_FPGA\phase_test\db\phase_test.(2).cnf.cdb PD_using_FPGA\phase_test\db\phase_test.(2).cnf.hdb PD_using_FPGA\phase_test\db\phase_test.(3).cnf.cdb PD_using_FPGA\phase_test\db\phase_test.(3).cnf.hdb PD_using_FPGA\phase_test\db\phase_test.(4).cnf.cdb PD_using_FPGA\phase_test\db\phase_test.(4).cnf.hdb PD_using_FPGA\phase_test\db\phase_test.(5).cnf.cdb PD_using_FPGA\phase_test\db\phase_test.(5).cnf.hdb PD_using_FPGA\phase_test\db\phase_test.(6).cnf.cdb PD_using_FPGA\phase_test\db\phase_test.(6).cnf.hdb PD_using_FPGA\phase_test\db\phase_test.(7).cnf.cdb PD_using_FPGA\phase_test\db\phase_test.(7).cnf.hdb PD_using_FPGA\phase_test\db\phase_test.asm.qmsg PD_using_FPGA\phase_test\db\phase_test.cbx.xml PD_using_FPGA\phase_test\db\phase_test.cmp.cdb PD_using_FPGA\phase_test\db\phase_test.cmp.hdb PD_using_FPGA\phase_test\db\phase_test.cmp.kpt PD_using_FPGA\phase_test\db\phase_test.cmp.logdb PD_using_FPGA\phase_test\db\phase_test.cmp.rdb PD_using_FPGA\phase_test\db\phase_test.cmp.tdb PD_using_FPGA\phase_test\db\phase_test.cmp0.ddb PD_using_FPGA\phase_test\db\phase_test.dbp PD_using_FPGA\phase_test\db\phase_test.db_info PD_using_FPGA\phase_test\db\phase_test.eco.cdb PD_using_FPGA\phase_test\db\phase_test.eds_overflow PD_using_FPGA\phase_test\db\phase_test.fit.qmsg PD_using_FPGA\phase_test\db\phase_test.fnsim.hdb PD_using_FPGA\phase_test\db\phase_test.fnsim.qmsg PD_using_FPGA\phase_test\db\phase_test.hier_info PD_using_FPGA\phase_test\db\phase_test.hif PD_using_FPGA\phase_test\db\phase_test.map.cdb PD_using_FPGA\phase_test\db\phase_test.map.hdb PD_using_FPGA\phase_test\db\phase_test.map.logdb PD_using_FPGA\phase_test\db\phase_test.map.qmsg PD_using_FPGA\phase_test\db\phase_test.pre_map.cdb PD_using_FPGA\phase_test\db\phase_test.pre_map.hdb PD_using_FPGA\phase_test\db\phase_test.psp PD_using_FPGA\phase_test\db\phase_test.rtlv.hdb PD_using_FPGA\phase_test\db\phase_test.rtlv_sg.cdb PD_using_FPGA\phase_test\db\phase_test.rtlv_sg_swap.cdb PD_using_FPGA\phase_test\db\phase_test.sgdiff.cdb PD_using_FPGA\phase_test\db\phase_test.sgdiff.hdb PD_using_FPGA\phase_test\db\phase_test.signalprobe.cdb PD_using_FPGA\phase_test\db\phase_test.sim.hdb PD_using_FPGA\phase_test\db\phase_test.sim.qmsg PD_using_FPGA\phase_test\db\phase_test.sim.rdb PD_using_FPGA\phase_test\db\phase_test.sim.vwf PD_using_FPGA\phase_test\db\phase_test.sld_design_entry.sci PD_using_FPGA\phase_test\db\phase_test.sld_design_entry_dsc.sci PD_using_FPGA\phase_test\db\phase_test.smp_dump.txt PD_using_FPGA\phase_test\db\phase_test.syn_hier_info PD_using_FPGA\phase_test\db\phase_test.tan.qmsg PD_using_FPGA\phase_test\db\wed.zsf PD_using_FPGA\phase_test\db PD_using_FPGA\phase_test PD_using_FPGA