文件名称:masterspiverilog
介绍说明－－下载内容均来自于网络，请自行研究使用
spi总线控制器的fpga实现 verilog源代码及测试-spi bus controller realize the FPGA Verilog source code and test
相关搜索： spi
verilog
verilog
spi
SPI
verilog
SPI
VHDL
SPI
FPGA
fpga
SPI
Verilog
SPI
SPI
Verilog
SPI
verilog
code
verilog
verilog
spi
SPI
verilog
SPI
VHDL
SPI
FPGA
fpga
SPI
Verilog
SPI
SPI
Verilog
SPI
verilog
code
(系统自动生成,下载前可以参看下载内容)
下载文件列表
SimpleSpi
.........\Bench
.........\.....\spi_slave_model.v
.........\.....\tst_bench_top.v
.........\.....\wb_master_model.v
.........\doc
.........\...\simple_spi.doc
.........\...\simple_spi.pdf
.........\Rtl
.........\...\fifo4.v
.........\...\simple_spi_top.v
.........\sim
.........\...\bin
.........\...\...\Makefile.1;content-type=text%2Fplain.txt
.........\...\run
.........\...\...\Makefile.1;content-type=text%2Fplain.txt
.........\...\...\ncsim.log
.........\...\...\ncvlog.log
.........\...\...\simvision.sv.txt
.........\...\...\stdout.log
.........\...\...\waves.do.txt
.........\Bench
.........\.....\spi_slave_model.v
.........\.....\tst_bench_top.v
.........\.....\wb_master_model.v
.........\doc
.........\...\simple_spi.doc
.........\...\simple_spi.pdf
.........\Rtl
.........\...\fifo4.v
.........\...\simple_spi_top.v
.........\sim
.........\...\bin
.........\...\...\Makefile.1;content-type=text%2Fplain.txt
.........\...\run
.........\...\...\Makefile.1;content-type=text%2Fplain.txt
.........\...\...\ncsim.log
.........\...\...\ncvlog.log
.........\...\...\simvision.sv.txt
.........\...\...\stdout.log
.........\...\...\waves.do.txt