文件名称:FIR
介绍说明－－下载内容均来自于网络，请自行研究使用
ＦＰＧＡ实现数字滤波器，基于硬件描述语言ＶＥＲＩＬＯＧ ＨＤＬ，顶层文件ＦＩＲ．Ｖ-FPGA realization of digital filters, based on the hardware descr iption language VERILOG HDL, the top-level file FIR. V
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FIR
...\add3.v
...\adder16.v
...\adder4.v
...\adder8.v
...\adderbu.v
...\alu.v
...\boothcode.v
...\fir.v
...\fir_control.v
...\fir_tp.v
...\mux16_2.v
...\mux8_1.v
...\shift.v
...\trigger1.v
...\trigger2.v
...\wallace.v
...\add3.v
...\adder16.v
...\adder4.v
...\adder8.v
...\adderbu.v
...\alu.v
...\boothcode.v
...\fir.v
...\fir_control.v
...\fir_tp.v
...\mux16_2.v
...\mux8_1.v
...\shift.v
...\trigger1.v
...\trigger2.v
...\wallace.v