文件名称:fpga-jpeg-verilog
- 所属分类：
- 其他嵌入式/单片机内容
- 资源属性：
- [Windows] [程序]
- 上传时间：
- 2012-11-26
- 文件大小：
- 102kb
- 下载次数：
- 0次
- 提 供 者：
- y***
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
fpga-jpeg-verilog在fpga平台使用verilog语言进行jpeg算法实现-fpga-jpeg-verilog FPGA platform used in the Verilog language Algorithm jpeg
相关搜索： jpeg
verilog
verilog
jpeg
fpga
jpeg
JPEG
FPGA
jpeg
verilog
FPGA
fpga
算法
jpeg
verilog
jpEG
verilog
jp
designing
a
jpeg
fpga
verilog
verilog
jpeg
fpga
jpeg
JPEG
FPGA
jpeg
verilog
FPGA
fpga
算法
jpeg
verilog
jpEG
verilog
jp
designing
a
jpeg
fpga
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fpga-jpeg-verilog
.................\dct
.................\...\dct.v
.................\...\dctu.v
.................\...\dctub.v
.................\...\dct_bench
.................\...\.........\bench_top.v
.................\...\dct_cos_table.v
.................\...\dct_mac.v
.................\...\dct_syn.v
.................\...\fdct.v
.................\...\huffman
.................\...\.......\bench
.................\...\.......\.....\bench_top.v
.................\...\.......\.....\generic_dpram.v
.................\...\.......\.....\generic_fifo_lfsr.v
.................\...\.......\.....\lfsr.v
.................\...\.......\.....\timescale.v
.................\...\.......\huffman_dec.v
.................\...\.......\huffman_enc.v
.................\...\.......\huffman_tables.v
.................\...\ro_cnt.v
.................\...\rtl_sim
.................\...\.......\Makefile.txt
.................\...\ud_cnt.v
.................\...\zigzag.v
.................\jpeg
.................\....\bench_top
.................\....\.........\jpeg_encoder.v
.................\....\jpeg_encoder.v
.................\....\sim
.................\....\...\cds.lib
.................\....\...\hdl.var
.................\....\...\Makefile.txt
.................\qnr
.................\...\attic
.................\...\.....\div.v
.................\...\.....\div_us.v
.................\...\.....\ro_cnt.v
.................\...\.....\ud_cnt.v
.................\...\bench
.................\...\.....\bench_div_top.v
.................\...\.....\bench_qnr_top.v
.................\...\.....\timescale.v
.................\...\div_su.v
.................\...\div_uu.v
.................\...\jpeg_qnr.v
.................\rgb2ycrcb
.................\.........\modelsim.ini
.................\.........\rgb2ycrcb
.................\.........\.........\_info
.................\.........\rgb2ycrcb.mpf
.................\.........\rgb2ycrcb.v
.................\.........\rgb2ycrcb_testbench.v
.................\.........\rgb2ycrcb_webAddress.txt
.................\.........\tcl_stacktrace.txt
.................\.........\transcript
.................\.........\work
.................\.........\....\_info
.................\run_length_coding
.................\.................\attic
.................\.................\.....\jpeg_rle2.v
.................\.................\bench
.................\.................\.....\bench.v.txt
.................\.................\jpeg_rle.v
.................\.................\jpeg_rle1.v
.................\.................\jpeg_rzs.v
.................\dct
.................\...\dct.v
.................\...\dctu.v
.................\...\dctub.v
.................\...\dct_bench
.................\...\.........\bench_top.v
.................\...\dct_cos_table.v
.................\...\dct_mac.v
.................\...\dct_syn.v
.................\...\fdct.v
.................\...\huffman
.................\...\.......\bench
.................\...\.......\.....\bench_top.v
.................\...\.......\.....\generic_dpram.v
.................\...\.......\.....\generic_fifo_lfsr.v
.................\...\.......\.....\lfsr.v
.................\...\.......\.....\timescale.v
.................\...\.......\huffman_dec.v
.................\...\.......\huffman_enc.v
.................\...\.......\huffman_tables.v
.................\...\ro_cnt.v
.................\...\rtl_sim
.................\...\.......\Makefile.txt
.................\...\ud_cnt.v
.................\...\zigzag.v
.................\jpeg
.................\....\bench_top
.................\....\.........\jpeg_encoder.v
.................\....\jpeg_encoder.v
.................\....\sim
.................\....\...\cds.lib
.................\....\...\hdl.var
.................\....\...\Makefile.txt
.................\qnr
.................\...\attic
.................\...\.....\div.v
.................\...\.....\div_us.v
.................\...\.....\ro_cnt.v
.................\...\.....\ud_cnt.v
.................\...\bench
.................\...\.....\bench_div_top.v
.................\...\.....\bench_qnr_top.v
.................\...\.....\timescale.v
.................\...\div_su.v
.................\...\div_uu.v
.................\...\jpeg_qnr.v
.................\rgb2ycrcb
.................\.........\modelsim.ini
.................\.........\rgb2ycrcb
.................\.........\.........\_info
.................\.........\rgb2ycrcb.mpf
.................\.........\rgb2ycrcb.v
.................\.........\rgb2ycrcb_testbench.v
.................\.........\rgb2ycrcb_webAddress.txt
.................\.........\tcl_stacktrace.txt
.................\.........\transcript
.................\.........\work
.................\.........\....\_info
.................\run_length_coding
.................\.................\attic
.................\.................\.....\jpeg_rle2.v
.................\.................\bench
.................\.................\.....\bench.v.txt
.................\.................\jpeg_rle.v
.................\.................\jpeg_rle1.v
.................\.................\jpeg_rzs.v