文件名称:hdlc
介绍说明－－下载内容均来自于网络，请自行研究使用
该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl fr a me transmission protocol HDLC fr a me of this generation- Codes will be used QUATUSII people should know how to use, in the hope of giving you helpful
相关搜索： hdlc
hdlc
verilog
hdlc
veril
verilog
HDLC
verilog
Verilog
fr a me
verilog
hdlc
Verilog
Protocol
hdlc
rar
verilog
fr a me
based
hdlc
verilog
hdlc
veril
verilog
HDLC
verilog
Verilog
fr a me
verilog
hdlc
Verilog
Protocol
hdlc
rar
verilog
fr a me
based
(系统自动生成,下载前可以参看下载内容)
下载文件列表
hdlc
....\cmp_state.ini
....\control.v
....\crc1.v
....\db
....\..\add_sub_4rh.tdf
....\..\add_sub_6rh.tdf
....\..\add_sub_7rh.tdf
....\..\hdlc.asm.qmsg
....\..\hdlc.cbx.xml
....\..\hdlc.cmp.cdb
....\..\hdlc.cmp.hdb
....\..\hdlc.cmp.rdb
....\..\hdlc.cmp.tdb
....\..\hdlc.cmp0.ddb
....\..\hdlc.db_info
....\..\hdlc.eco.cdb
....\..\hdlc.eds_overflow
....\..\hdlc.fit.qmsg
....\..\hdlc.fnsim.cdb
....\..\hdlc.fnsim.hdb
....\..\hdlc.hier_info
....\..\hdlc.hif
....\..\hdlc.map.cdb
....\..\hdlc.map.hdb
....\..\hdlc.map.qmsg
....\..\hdlc.pre_map.cdb
....\..\hdlc.pre_map.hdb
....\..\hdlc.psp
....\..\hdlc.rtlv.hdb
....\..\hdlc.rtlv_sg.cdb
....\..\hdlc.rtlv_sg_swap.cdb
....\..\hdlc.sgdiff.cdb
....\..\hdlc.sgdiff.hdb
....\..\hdlc.signalprobe.cdb
....\..\hdlc.sim.hdb
....\..\hdlc.sim.qmsg
....\..\hdlc.sim.rdb
....\..\hdlc.sim.vwf
....\..\hdlc.sld_design_entry.sci
....\..\hdlc.sld_design_entry_dsc.sci
....\..\hdlc.smp_dump.txt
....\..\hdlc.syn_hier_info
....\..\hdlc.tan.qmsg
....\..\hdlc_cmp.qrpt
....\..\hdlc_sim.qrpt
....\..\mux_2ec.tdf
....\..\mux_3ec.tdf
....\..\mux_jcc.tdf
....\..\mux_toc.tdf
....\flag1.v
....\free.v
....\hdlc.asm.rpt
....\hdlc.done
....\hdlc.fit.eqn
....\hdlc.fit.rpt
....\hdlc.fit.summary
....\hdlc.flow.rpt
....\hdlc.map.eqn
....\hdlc.map.rpt
....\hdlc.map.summary
....\hdlc.pin
....\hdlc.qpf
....\hdlc.qsf
....\hdlc.qws
....\hdlc.sim.rpt
....\hdlc.tan.rpt
....\hdlc.tan.summary
....\hdlc.v
....\hdlc.vwf
....\mux3.v
....\serv_req_info.txt
....\shift32.v
....\test501.v
....\tian0.v
....\cmp_state.ini
....\control.v
....\crc1.v
....\db
....\..\add_sub_4rh.tdf
....\..\add_sub_6rh.tdf
....\..\add_sub_7rh.tdf
....\..\hdlc.asm.qmsg
....\..\hdlc.cbx.xml
....\..\hdlc.cmp.cdb
....\..\hdlc.cmp.hdb
....\..\hdlc.cmp.rdb
....\..\hdlc.cmp.tdb
....\..\hdlc.cmp0.ddb
....\..\hdlc.db_info
....\..\hdlc.eco.cdb
....\..\hdlc.eds_overflow
....\..\hdlc.fit.qmsg
....\..\hdlc.fnsim.cdb
....\..\hdlc.fnsim.hdb
....\..\hdlc.hier_info
....\..\hdlc.hif
....\..\hdlc.map.cdb
....\..\hdlc.map.hdb
....\..\hdlc.map.qmsg
....\..\hdlc.pre_map.cdb
....\..\hdlc.pre_map.hdb
....\..\hdlc.psp
....\..\hdlc.rtlv.hdb
....\..\hdlc.rtlv_sg.cdb
....\..\hdlc.rtlv_sg_swap.cdb
....\..\hdlc.sgdiff.cdb
....\..\hdlc.sgdiff.hdb
....\..\hdlc.signalprobe.cdb
....\..\hdlc.sim.hdb
....\..\hdlc.sim.qmsg
....\..\hdlc.sim.rdb
....\..\hdlc.sim.vwf
....\..\hdlc.sld_design_entry.sci
....\..\hdlc.sld_design_entry_dsc.sci
....\..\hdlc.smp_dump.txt
....\..\hdlc.syn_hier_info
....\..\hdlc.tan.qmsg
....\..\hdlc_cmp.qrpt
....\..\hdlc_sim.qrpt
....\..\mux_2ec.tdf
....\..\mux_3ec.tdf
....\..\mux_jcc.tdf
....\..\mux_toc.tdf
....\flag1.v
....\free.v
....\hdlc.asm.rpt
....\hdlc.done
....\hdlc.fit.eqn
....\hdlc.fit.rpt
....\hdlc.fit.summary
....\hdlc.flow.rpt
....\hdlc.map.eqn
....\hdlc.map.rpt
....\hdlc.map.summary
....\hdlc.pin
....\hdlc.qpf
....\hdlc.qsf
....\hdlc.qws
....\hdlc.sim.rpt
....\hdlc.tan.rpt
....\hdlc.tan.summary
....\hdlc.v
....\hdlc.vwf
....\mux3.v
....\serv_req_info.txt
....\shift32.v
....\test501.v
....\tian0.v