文件名称:usb1_funct
介绍说明－－下载内容均来自于网络，请自行研究使用
usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
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源代码
usb1
1
verilog
usb
Verilog
usb1_fun
Verilog
source
code
usb
code
source
verilog
testbench
verilog
usb
Verilog
源代码
usb1
1
verilog
usb
Verilog
usb1_fun
Verilog
source
code
usb
code
source
verilog
testbench
(系统自动生成,下载前可以参看下载内容)
下载文件列表
usb1_funct
..........\bench
..........\.....\verilog
..........\.....\.......\tests.v
..........\.....\.......\tests_lib.v
..........\.....\.......\test_bench_top.v
..........\.....\.......\timescale.v
..........\doc
..........\...\README.txt
..........\...\success_story.txt
..........\rtl
..........\...\verilog
..........\...\.......\timescale.v
..........\...\.......\usb1_core.v
..........\...\.......\usb1_crc16.v
..........\...\.......\usb1_crc5.v
..........\...\.......\usb1_ctrl.v
..........\...\.......\usb1_defines.v
..........\...\.......\usb1_fifo2.v
..........\...\.......\usb1_idma.v
..........\...\.......\usb1_pa.v
..........\...\.......\usb1_pd.v
..........\...\.......\usb1_pe.v
..........\...\.......\usb1_pl.v
..........\...\.......\usb1_rom1.v
..........\...\.......\usb1_utmi_if.v
..........\sim
..........\...\rtl_sim
..........\...\.......\bin
..........\...\.......\...\Makefile
..........\...\.......\run
..........\...\.......\...\Makefile
..........\...\.......\...\waves
..........\...\.......\...\.....\waves.do
..........\bench
..........\.....\verilog
..........\.....\.......\tests.v
..........\.....\.......\tests_lib.v
..........\.....\.......\test_bench_top.v
..........\.....\.......\timescale.v
..........\doc
..........\...\README.txt
..........\...\success_story.txt
..........\rtl
..........\...\verilog
..........\...\.......\timescale.v
..........\...\.......\usb1_core.v
..........\...\.......\usb1_crc16.v
..........\...\.......\usb1_crc5.v
..........\...\.......\usb1_ctrl.v
..........\...\.......\usb1_defines.v
..........\...\.......\usb1_fifo2.v
..........\...\.......\usb1_idma.v
..........\...\.......\usb1_pa.v
..........\...\.......\usb1_pd.v
..........\...\.......\usb1_pe.v
..........\...\.......\usb1_pl.v
..........\...\.......\usb1_rom1.v
..........\...\.......\usb1_utmi_if.v
..........\sim
..........\...\rtl_sim
..........\...\.......\bin
..........\...\.......\...\Makefile
..........\...\.......\run
..........\...\.......\...\Makefile
..........\...\.......\...\waves
..........\...\.......\...\.....\waves.do