文件名称:8.10
介绍说明－－下载内容均来自于网络，请自行研究使用
强烈推荐下载,verilog状态机实例.可以在modelsim下运行.
-strongly recommend downloading Verilog state machine example. In modelsim running.
-strongly recommend downloading Verilog state machine example. In modelsim running.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
8.10
....\dflop.cr.mti
....\dflop.mpf
....\dflop.v
....\dflop.v.bak
....\test.v
....\test.v.bak
....\vsim.wlf
....\work
....\....\dflop
....\....\.....\verilog.asm
....\....\.....\_primary.dat
....\....\.....\_primary.vhd
....\....\shifter
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\test
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\_info
....\dflop.cr.mti
....\dflop.mpf
....\dflop.v
....\dflop.v.bak
....\test.v
....\test.v.bak
....\vsim.wlf
....\work
....\....\dflop
....\....\.....\verilog.asm
....\....\.....\_primary.dat
....\....\.....\_primary.vhd
....\....\shifter
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\test
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\_info