文件名称:uart_verilog hdl
- 所属分类:
- 源码下载
- 资源属性:
- [VHDL] [源码]
- 上传时间:
- 2011-12-12
- 文件大小:
- 373.64kb
- 下载次数:
- 0次
- 提 供 者:
- chenweihdu
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
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FPGA中串口的实现,基于verilog hdl
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : uartverilog.rar 列表 uartverilog/my_uart_rx.v uartverilog/my_uart_top.cdf uartverilog/my_uart_top.done uartverilog/my_uart_top.dpf uartverilog/my_uart_top.fit.smsg uartverilog/my_uart_top.fit.summary uartverilog/my_uart_top.jpg uartverilog/my_uart_top.map.smsg uartverilog/my_uart_top.map.summary uartverilog/my_uart_top.pin uartverilog/my_uart_top.pof uartverilog/my_uart_top.qpf uartverilog/my_uart_top.qsf uartverilog/my_uart_top.tan.summary uartverilog/my_uart_top.v uartverilog/my_uart_top.v.bak uartverilog/my_uart_top_assignment_defaults.qdf uartverilog/my_uart_tx.v uartverilog/speed_select.v uartverilog/transcript uartverilog/my_uart_top.map.rpt uartverilog/my_uart_top.fit.rpt uartverilog/my_uart_top.asm.rpt uartverilog/my_uart_top.tan.rpt uartverilog/my_uart_top.flow.rpt uartverilog/my_uart_top.vwf uartverilog/my_uart_top.sim.rpt uartverilog/incremental_db/README uartverilog/incremental_db/compiled_partitions/my_uart_top.root_partition.map.kpt uartverilog/db/my_uart_top.map.logdb uartverilog/db/my_uart_top.sgdiff.cdb uartverilog/db/my_uart_top.(1).cnf.cdb uartverilog/db/my_uart_top.(1).cnf.hdb uartverilog/db/my_uart_top.(2).cnf.cdb uartverilog/db/my_uart_top.(2).cnf.hdb uartverilog/db/my_uart_top.(3).cnf.cdb uartverilog/db/my_uart_top.(3).cnf.hdb uartverilog/db/my_uart_top.asm.qmsg uartverilog/db/my_uart_top.pre_map.hdb uartverilog/db/my_uart_top.cbx.xml uartverilog/db/my_uart_top.pre_map.cdb uartverilog/db/my_uart_top.sgdiff.hdb uartverilog/db/my_uart_top.cmp.kpt uartverilog/db/my_uart_top.fit.qmsg uartverilog/db/mux_cbc.tdf uartverilog/db/my_uart_top.sld_design_entry_dsc.sci uartverilog/db/wed.wsf uartverilog/db/my_uart_top.cmp.logdb uartverilog/db/my_uart_top.db_info uartverilog/db/my_uart_top.map.cdb uartverilog/db/my_uart_top.tan.qmsg uartverilog/db/my_uart_top.hier_info uartverilog/db/my_uart_top.hif uartverilog/db/my_uart_top.map.hdb uartverilog/db/prev_cmp_my_uart_top.map.qmsg uartverilog/db/my_uart_top.asm_labs.ddb uartverilog/db/my_uart_top.cmp.tdb uartverilog/db/my_uart_top.cmp.hdb uartverilog/db/my_uart_top.fnsim.qmsg uartverilog/db/my_uart_top.cmp.rdb uartverilog/db/my_uart_top.tis_db_list.ddb uartverilog/db/my_uart_top.rpp.qmsg uartverilog/db/my_uart_top.sgate.rvd uartverilog/db/my_uart_top.cmp0.ddb uartverilog/db/my_uart_top.cmp.cdb uartverilog/db/my_uart_top.sgate_sm.rvd uartverilog/db/prev_cmp_my_uart_top.fit.qmsg uartverilog/db/prev_cmp_my_uart_top.asm.qmsg uartverilog/db/prev_cmp_my_uart_top.tan.qmsg uartverilog/db/my_uart_top.syn_hier_info uartverilog/db/prev_cmp_my_uart_top.qmsg uartverilog/db/my_uart_top.sim.qmsg uartverilog/db/my_uart_top_global_asgn_op.abo uartverilog/db/my_uart_top.lpc.txt uartverilog/db/my_uart_top.lpc.html uartverilog/db/my_uart_top.lpc.rdb uartverilog/db/add_sub_flh.tdf uartverilog/db/add_sub_vmh.tdf uartverilog/db/my_uart_top.fnsim.cdb uartverilog/db/my_uart_top.fnsim.hdb uartverilog/db/my_uart_top.tmw_info uartverilog/db/my_uart_top.sim.hdb uartverilog/db/my_uart_top.simfam uartverilog/db/my_uart_top.eds_overflow uartverilog/db/my_uart_top.sim.cvwf uartverilog/db/my_uart_top.sim.rdb uartverilog/db/my_uart_top.map.qmsg uartverilog/db/my_uart_top.(0).cnf.cdb uartverilog/db/my_uart_top.(0).cnf.hdb uartverilog/db/my_uart_top.rtlv_sg.cdb uartverilog/db/my_uart_top.rtlv.hdb uartverilog/db/my_uart_top.rtlv_sg_swap.cdb uartverilog/db/my_uart_top.sld_design_entry.sci uartverilog/db/my_uart_top.eco.cdb uartverilog/my_uart_top.qws uartverilog/incremental_db/compiled_partitions uartverilog/incremental_db uartverilog/db uartverilog