压缩包 : 15883861stepper_motor_control_design_example.zip 列表
Application Note Disclaimer.doc
stepper_ip/component/
stepper_ip/constraint/
stepper_ip/coreconsole/
stepper_ip/designer/
stepper_ip/designer/impl1/
stepper_ip/designer/impl1/designer.log
stepper_ip/designer/impl1/designer_genhdl.log
stepper_ip/designer/impl1/simulation/
stepper_ip/designer/impl1/top_stepper_ip.adb
stepper_ip/designer/impl1/top_stepper_ip.dtf/
stepper_ip/designer/impl1/top_stepper_ip.dtf/verify.log
stepper_ip/designer/impl1/top_stepper_ip.ide_des
stepper_ip/designer/impl1/top_stepper_ip.stp
stepper_ip/designer/impl1/top_stepper_ip.tcl
stepper_ip/hdl/
stepper_ip/hdl/baud_clk_gen.v
stepper_ip/hdl/clkdiv_20M_to_10M.v
stepper_ip/hdl/clk_by_2.v
stepper_ip/hdl/clk_gen.v
stepper_ip/hdl/debounce.v
stepper_ip/hdl/debounce_blk.v
stepper_ip/hdl/divideby5.v
stepper_ip/hdl/div_by_16.v
stepper_ip/hdl/global.v
stepper_ip/hdl/mux_hw_sw.v
stepper_ip/hdl/PLL20_to_10.v
stepper_ip/hdl/pwm_gen_stepper.v
stepper_ip/hdl/recv_control.v
stepper_ip/hdl/serial.v
stepper_ip/hdl/stepper_clk_gen.v
stepper_ip/hdl/stepper_ip.v
stepper_ip/hdl/stepper_module.v
stepper_ip/hdl/top_serial.v
stepper_ip/hdl/top_stepper.v
stepper_ip/hdl/top_stepper_ip.v
stepper_ip/hdl/xmit_control.v
stepper_ip/phy_synthesis/
stepper_ip/Readme_stepper_ip.txt
stepper_ip/simulation/
stepper_ip/simulation/modelsim.ini
stepper_ip/simulation/modelsim.ini.sav
stepper_ip/simulation/modelsim.log
stepper_ip/simulation/postsynth/
stepper_ip/simulation/postsynth/baud_clk_gen/
stepper_ip/simulation/postsynth/baud_clk_gen/verilog.psm
stepper_ip/simulation/postsynth/baud_clk_gen/_primary.dat
stepper_ip/simulation/postsynth/baud_clk_gen/_primary.dbs
stepper_ip/simulation/postsynth/baud_clk_gen/_primary.vhd
stepper_ip/simulation/postsynth/clkdiv_20@m_to_10@m/
stepper_ip/simulation/postsynth/clkdiv_20@m_to_10@m/verilog.psm
stepper_ip/simulation/postsynth/clkdiv_20@m_to_10@m/_primary.dat
stepper_ip/simulation/postsynth/clkdiv_20@m_to_10@m/_primary.dbs
stepper_ip/simulation/postsynth/clkdiv_20@m_to_10@m/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2/
stepper_ip/simulation/postsynth/clk_by_2/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_1/
stepper_ip/simulation/postsynth/clk_by_2_10/
stepper_ip/simulation/postsynth/clk_by_2_10/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_10/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_10/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_10/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_11/
stepper_ip/simulation/postsynth/clk_by_2_11/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_11/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_11/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_11/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_12/
stepper_ip/simulation/postsynth/clk_by_2_12/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_12/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_12/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_12/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_13/
stepper_ip/simulation/postsynth/clk_by_2_13/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_13/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_13/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_13/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_14/
stepper_ip/simulation/postsynth/clk_by_2_14/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_14/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_14/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_14/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_15/
stepper_ip/simulation/postsynth/clk_by_2_15/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_15/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_15/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_15/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_16/
stepper_ip/simulation/postsynth/clk_by_2_16/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_16/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_16/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_16/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_17/
stepper_ip/simulation/postsynth/clk_by_2_17/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_17/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_17/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_17/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_1/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_1/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_1/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_1/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_2/
stepper_ip/simulation/postsynth/clk_by_2_21/
stepper_ip/simulation/postsynth/clk_by_2_21/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_21/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_21/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_21/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_22/
stepper_ip/simulation/postsynth/clk_by_2_22/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_22/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_22/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_22/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_23/
stepper_ip/simulation/postsynth/clk_by_2_23/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_23/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_23/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_23/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_24/
stepper_ip/simulation/postsynth/clk_by_2_24/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_24/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_24/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_24/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_25/
stepper_ip/simulation/postsynth/clk_by_2_25/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_25/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_25/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_25/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_2/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_2/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_2/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_2/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_3/
stepper_ip/simulation/postsynth/clk_by_2_3/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_3/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_3/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_3/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_4/
stepper_ip/simulation/postsynth/clk_by_2_4/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_4/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_4/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_4/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_5/
stepper_ip/simulation/postsynth/clk_by_2_5/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_5/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_5/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_5/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_6/
stepper_ip/simulation/postsynth/clk_by_2_6/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_6/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_6/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_6/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_7/
stepper_ip/simulation/postsynth/clk_by_2_7/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_7/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_7/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_7/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_8/
stepper_ip/simulation/postsynth/clk_by_2_8/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_8/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_8/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_8/_primary.vhd
stepper_ip/simulation/postsynth/clk_by_2_9/
stepper_ip/simulation/postsynth/clk_by_2_9/verilog.psm
stepper_ip/simulation/postsynth/clk_by_2_9/_primary.dat
stepper_ip/simulation/postsynth/clk_by_2_9/_primary.dbs
stepper_ip/simulation/postsynth/clk_by_2_9/_primary.vhd
stepper_ip/simulation/postsynth/clk_gen/
stepper_ip/simulation/postsynth/clk_gen/verilog.psm
stepper_ip/simulation/postsynth/clk_gen/_primary.dat
stepper_ip/simulation/postsynth/clk_gen/_primary.dbs
stepper_ip/simulation/postsynth/clk_gen/_primary.vhd
stepper_ip/simulation/postsynth/debounce_1/
stepper_ip/simulation/postsynth/debounce_1/verilog.psm
stepper_ip/simulation/postsynth/debounce_1/_primary.dat
stepper_ip/simulation/postsynth/debounce_1/_primary.dbs
stepper_ip/simulation/postsynth/debounce_1/_primary.vhd
stepper_ip/simulation/postsynth/debounce_1_1/
stepper_ip/simulation/postsynth/debounce_1_1/verilog.psm
stepper_ip/simulation/postsynth/debounce_1_1/_primary.dat
stepper_ip/simulation/postsynth/debounce_1_1/_primary.dbs
stepper_ip/simulation/postsynth/debounce_1_1/_primary.vhd
stepper_ip/simulation/postsynth/debounce_1_2/
stepper_ip/simulation/postsynth/debounce_1_2/verilog.psm
stepper_ip/simulation/postsynth/debounce_1_2/_primary.dat
stepper_ip/simulation/postsynth/debounce_1_2/_primary.dbs
stepper_ip/simulation/postsynth/debounce_1_2/_primary.vhd
stepper_ip/simulation/postsynth/debounce_1_3/
stepper_ip/simulation/postsynth/debounce_1_3/verilog.psm
stepper_ip/simulation/postsynth/debounce_1_3/_primary.dat
stepper_ip/simulation/postsynth/debounce_1_3/_primary.dbs
stepper_ip/simulation/postsynth/debounce_1_3/_primary.vhd
stepper_ip/simulation/postsynth/debounce_1_4/
stepper_ip/simulation/postsynth/debounce_1_4/verilog.psm
stepper_ip/simulation/postsynth/debounce_1_4/_primary.dat
stepper_ip/simulation/postsynth/debounce_1_4/_primary.dbs
stepper_ip/simulation/postsynth/debounce_1_4/_primary.vhd
stepper_ip/simulation/postsynth/debounce_1_5/
stepper_ip/simulation/postsynth/debounce_1_5/verilog.psm
stepper_ip/simulation/postsynth/debounce_1_5/_primary.dat
stepper_ip/simulation/postsynth/debounce_1_5/_primary.dbs
stepper_ip/simulation/postsynth/debounce_1_5/_primary.vhd
stepper_ip/simulation/postsynth/debounce_1_6/
stepper_ip/simulation/postsynth/debounce_1_6/verilog.psm
stepper_ip/simulation/postsynth/debounce_1_6/_primary.dat
stepper_ip/simulation/postsynth/debounce_1_6/_primary.dbs
stepper_ip/simulation/postsynth/debounce_1_6/_primary.vhd
stepper_ip/simulation/postsynth/debounce_1_7/
stepper_ip/simulation/postsynth/debounce_1_7/verilog.psm
stepper_ip/simulation/postsynth/debounce_1_7/_primary.dat
stepper_ip/simulation/postsynth/debounce_1_7/_primary.dbs
stepper_ip/simulation/postsynth/debounce_1_7/_primary.vhd
stepper_ip/simulation/postsynth/debounce_blk/
stepper_ip/simulation/postsynth/debounce_blk/verilog.psm
stepper_ip/simulation/postsynth/debounce_blk/_primary.dat
stepper_ip/simulation/postsynth/debounce_blk/_primary.dbs
stepper_ip/simulation/postsynth/debounce_blk/_primary.vhd
stepper_ip/simulation/postsynth/div_by_16/
stepper_ip/simulation/postsynth/div_by_16/verilog.psm
stepper_ip/simulation/postsynth/div_by_16/_primary.dat
stepper_ip/simulation/postsynth/div_by_16/_primary.dbs
stepper_ip/simulation/postsynth/div_by_16/_primary.vhd
stepper_ip/simulation/postsynth/mux_hw_sw/
stepper_ip/simulation/postsynth/mux_hw_sw/verilog.psm
stepper_ip/simulation/postsynth/mux_hw_sw/_primary.dat
stepper_ip/simulation/postsynth/mux_hw_sw/_primary.dbs
stepper_ip/simulation/postsynth/mux_hw_sw/_primary.vhd
stepper_ip/simulation/postsynth/pwm_gen_stepper/
stepper_ip/simulation/postsynth/pwm_gen_stepper/verilog.psm
stepper_ip/simulation/postsynth/pwm_gen_stepper/_primary.dat
stepper_ip/simulation/postsynth/pwm_gen_stepper/_primary.dbs
stepper_ip/simulation/postsynth/pwm_gen_stepper/_primary.vhd
stepper_ip/simulation/postsynth/recv_control/
stepper_ip/simulation/postsynth/recv_control/verilog.psm
stepper_ip/simulation/postsynth/recv_control/_primary.dat
stepper_ip/simulation/postsynth/recv_control/_primary.dbs
stepper_ip/simulation/postsynth/recv_control/_primary.vhd
stepper_ip/simulation/postsynth/serial/
stepper_ip/simulation/postsynth/serial/verilog.psm
stepper_ip/simulation/postsynth/serial/_primary.dat
stepper_ip/simulation/postsynth/serial/_primary.dbs
stepper_ip/simulation/postsynth/serial/_primary.vhd
stepper_ip/simulation/postsynth/stepper_clk_gen/
stepper_ip/simulation/postsynth/stepper_clk_gen/verilog.psm
stepper_ip/simulation/postsynth/stepper_clk_gen/_primary.dat
stepper_ip/simulation/postsynth/stepper_clk_gen/_primary.dbs
stepper_ip/simulation/postsynth/stepper_clk_gen/_primary.vhd
stepper_ip/simulation/postsynth/stepper_ip/
stepper_ip/simulation/postsynth/stepper_ip/verilog.psm
stepper_ip/simulation/postsynth/stepper_ip/_primary.dat
stepper_ip/simulation/postsynth/stepper_ip/_primary.dbs
stepper_ip/simulation/postsynth/stepper_ip/_primary.vhd
stepper_ip/simulation/postsynth/stepper_module/
stepper_ip/simulation/postsynth/stepper_module/verilog.psm
stepper_ip/simulation/postsynth/stepper_module/_primary.dat
stepper_ip/simulation/postsynth/stepper_module/_primary.dbs
stepper_ip/simulation/postsynth/stepper_module/_primary.vhd
stepper_ip/simulation/postsynth/testbench/
stepper_ip/simulation/postsynth/testbench/verilog.psm
stepper_ip/simulation/postsynth/testbench/_primary.dat
stepper_ip/simulation/postsynth/testbench/_primary.dbs
stepper_ip/simulation/postsynth/testbench/_primary.vhd
stepper_ip/simulation/postsynth/top_serial/
stepper_ip/simulation/postsynth/top_serial/verilog.psm
stepper_ip/simulation/postsynth/top_serial/_primary.dat
stepper_ip/simulation/postsynth/top_serial/_primary.dbs
stepper_ip/simulation/postsynth/top_serial/_primary.vhd
stepper_ip/simulation/postsynth/top_stepper/
stepper_ip/simulation/postsynth/top_stepper/verilog.psm
stepper_ip/simulation/postsynth/top_stepper/_primary.dat
stepper_ip/simulation/postsynth/top_stepper/_primary.dbs
stepper_ip/simulation/postsynth/top_stepper/_primary.vhd
stepper_ip/simulation/postsynth/top_stepper_ip/
stepper_ip/simulation/postsynth/top_stepper_ip/verilog.psm
stepper_ip/simulation/postsynth/top_stepper_ip/_primary.dat
stepper_ip/simulation/postsynth/top_stepper_ip/_primary.dbs
stepper_ip/simulation/postsynth/top_stepper_ip/_primary.vhd
stepper_ip/simulation/postsynth/xmit_control/
stepper_ip/simulation/postsynth/xmit_control/verilog.psm
stepper_ip/simulation/postsynth/xmit_control/_primary.dat
stepper_ip/simulation/postsynth/xmit_control/_primary.dbs
stepper_ip/simulation/postsynth/xmit_control/_primary.vhd
stepper_ip/simulation/postsynth/_info
stepper_ip/simulation/postsynth/_temp/
stepper_ip/simulation/presynth/
stepper_ip/simulation/presynth/baud_clk_gen/
stepper_ip/simulation/presynth/baud_clk_gen/verilog.psm
stepper_ip/simulation/presynth/baud_clk_gen/_primary.dat
stepper_ip/simulation/presynth/baud_clk_gen/_primary.dbs
stepper_ip/simulation/presynth/baud_clk_gen/_primary.vhd
stepper_ip/simulation/presynth/clkdiv_20@m_to_10@m/
stepper_ip/simulation/presynth/clkdiv_20@m_to_10@m/verilog.psm
stepper_ip/simulation/presynth/clkdiv_20@m_to_10@m/_primary.dat
stepper_ip/simulation/presynth/clkdiv_20@m_to_10@m/_primary.dbs
stepper_ip/simulation/presynth/clkdiv_20@m_to_10@m/_primary.vhd
stepper_ip/simulation/presynth/clk_by_2/
stepper_ip/simulation/presynth/clk_by_2/verilog.psm
stepper_ip/simulation/presynth/clk_by_2/_primary.dat
stepper_ip/simulation/presynth/clk_by_2/_primary.dbs
stepper_ip/simulation/presynth/clk_by_2/_primary.vhd
stepper_ip/simulation/presynth/clk_gen/
stepper_ip/simulation/presynth/clk_gen/verilog.psm
stepper_ip/simulation/presynth/clk_gen/_primary.dat
stepper_ip/simulation/presynth/clk_gen/_primary.dbs
stepper_ip/simulation/presynth/clk_gen/_primary.vhd
stepper_ip/simulation/presynth/debounce/
stepper_ip/simulation/presynth/debounce/verilog.psm
stepper_ip/simulation/presynth/debounce/_primary.dat
stepper_ip/simulation/presynth/debounce/_primary.dbs
stepper_ip/simulation/presynth/debounce/_primary.vhd
stepper_ip/simulation/presynth/debounce_blk/
stepper_ip/simulation/presynth/debounce_blk/verilog.psm
stepper_ip/simulation/presynth/debounce_blk/_primary.dat
stepper_ip/simulation/presynth/debounce_blk/_primary.dbs
stepper_ip/simulation/presynth/debounce_blk/_primary.vhd
stepper_ip/simulation/presynth/divideby5/
stepper_ip/simulation/presynth/divideby5/verilog.psm
stepper_ip/simulation/presynth/divideby5/_primary.dat
stepper_ip/simulation/presynth/divideby5/_primary.dbs
stepper_ip/simulation/presynth/divideby5/_primary.vhd
stepper_ip/simulation/presynth/div_by_16/
stepper_ip/simulation/presynth/div_by_16/verilog.psm
stepper_ip/simulation/presynth/div_by_16/_primary.dat
stepper_ip/simulation/presynth/div_by_16/_primary.dbs
stepper_ip/simulation/presynth/div_by_16/_primary.vhd
stepper_ip/simulation/presynth/mux_hw_sw/
stepper_ip/simulation/presynth/mux_hw_sw/verilog.psm
stepper_ip/simulation/presynth/mux_hw_sw/_primary.dat
stepper_ip/simulation/presynth/mux_hw_sw/_primary.dbs
stepper_ip/simulation/presynth/mux_hw_sw/_primary.vhd
stepper_ip/simulation/presynth/pwm_gen_stepper/
stepper_ip/simulation/presynth/pwm_gen_stepper/verilog.psm
stepper_ip/simulation/presynth/pwm_gen_stepper/_primary.dat
stepper_ip/simulation/presynth/pwm_gen_stepper/_primary.dbs
stepper_ip/simulation/presynth/pwm_gen_stepper/_primary.vhd
stepper_ip/simulation/presynth/recv_control/
stepper_ip/simulation/presynth/recv_control/verilog.psm
stepper_ip/simulation/presynth/recv_control/_primary.dat
stepper_ip/simulation/presynth/recv_control/_primary.dbs
stepper_ip/simulation/presynth/recv_control/_primary.vhd
stepper_ip/simulation/presynth/serial/
stepper_ip/simulation/presynth/serial/verilog.psm
stepper_ip/simulation/presynth/serial/_primary.dat
stepper_ip/simulation/presynth/serial/_primary.dbs
stepper_ip/simulation/presynth/serial/_primary.vhd
stepper_ip/simulation/presynth/stepper_clk_gen/
stepper_ip/simulation/presynth/stepper_clk_gen/verilog.psm
stepper_ip/simulation/presynth/stepper_clk_gen/_primary.dat
stepper_ip/simulation/presynth/stepper_clk_gen/_primary.dbs
stepper_ip/simulation/presynth/stepper_clk_gen/_primary.vhd
stepper_ip/simulation/presynth/stepper_ip/
stepper_ip/simulation/presynth/stepper_ip/verilog.psm
stepper_ip/simulation/presynth/stepper_ip/_primary.dat
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stepper_ip/simulation/presynth/stepper_ip/_primary.vhd
stepper_ip/simulation/presynth/stepper_module/
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stepper_ip/simulation/presynth/stepper_module/_primary.vhd
stepper_ip/simulation/presynth/testbench/
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stepper_ip/simulation/presynth/top_serial/
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stepper_ip/simulation/presynth/top_serial/_primary.dbs
stepper_ip/simulation/presynth/top_serial/_primary.vhd
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stepper_ip/simulation/presynth/top_stepper/_primary.vhd
stepper_ip/simulation/presynth/top_stepper_ip/
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stepper_ip/simulation/presynth/top_stepper_ip/_primary.vhd
stepper_ip/simulation/presynth/xmit_control/
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stepper_ip/simulation/presynth/_info
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stepper_ip/simulation/run.do
stepper_ip/simulation/wave.do
stepper_ip/smartgen/
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stepper_ip/stepper_ip_libero_project.prj
stepper_ip/stimulus/
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stepper_ip/synthesis/
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stepper_ip/synthesis/backup/
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stepper_ip/synthesis/layer0.sro
stepper_ip/synthesis/layer0.tlg
stepper_ip/synthesis/layer1.info
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stepper_ip/synthesis/run_options.txt
stepper_ip/synthesis/stdout.log
stepper_ip/synthesis/syntax.log
stepper_ip/synthesis/syntmp/
stepper_ip/synthesis/syntmp/sap.log
stepper_ip/synthesis/syntmp/top_stepper_ip.msg
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stepper_ip/synthesis/top_stepper_ip_sdc.sdc
stepper_ip/synthesis/top_stepper_ip_syn.prd
stepper_ip/synthesis/top_stepper_ip_syn.prj
stepper_ip/synthesis/traplog.tlg
stepper_ip/synthesis/_mh_info
stepper_ip/synthesis/_verilog_hintfile
stepper_ip/viewdraw/
stepper_ip/viewdraw/sch/
stepper_ip/viewdraw/sym/
stepper_ip/viewdraw/vf/
stepper_ip/viewdraw/vf/project.lst
stepper_ip/viewdraw/viewdraw.ini
stepper_ip/viewdraw/wir/