文件名称:stepper_motor_control_design_example
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步进电机 VHDL 控制，整步 半步 细分 actel FPGA使用-VHDL stepper motor control, whole-step half-step breakdown of the use of actel FPGA
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下载文件列表
Application Note Disclaimer.doc
stepper_ip
..........\component
..........\constraint
..........\coreconsole
..........\designer
..........\........\impl1
..........\........\.....\designer.log
..........\........\.....\designer_genhdl.log
..........\........\.....\simulation
..........\........\.....\top_stepper_ip.adb
..........\........\.....\top_stepper_ip.dtf
..........\........\.....\..................\verify.log
..........\........\.....\top_stepper_ip.ide_des
..........\........\.....\top_stepper_ip.stp
..........\........\.....\top_stepper_ip.tcl
..........\hdl
..........\...\baud_clk_gen.v
..........\...\clkdiv_20M_to_10M.v
..........\...\clk_by_2.v
..........\...\clk_gen.v
..........\...\debounce.v
..........\...\debounce_blk.v
..........\...\divideby5.v
..........\...\div_by_16.v
..........\...\global.v
..........\...\mux_hw_sw.v
..........\...\PLL20_to_10.v
..........\...\pwm_gen_stepper.v
..........\...\recv_control.v
..........\...\serial.v
..........\...\stepper_clk_gen.v
..........\...\stepper_ip.v
..........\...\stepper_module.v
..........\...\top_serial.v
..........\...\top_stepper.v
..........\...\top_stepper_ip.v
..........\...\xmit_control.v
..........\phy_synthesis
..........\Readme_stepper_ip.txt
..........\simulation
..........\..........\modelsim.ini
..........\..........\modelsim.ini.sav
..........\..........\modelsim.log
..........\..........\postsynth
..........\..........\.........\baud_clk_gen
..........\..........\.........\............\verilog.psm
..........\..........\.........\............\_primary.dat
..........\..........\.........\............\_primary.dbs
..........\..........\.........\............\_primary.vhd
..........\..........\.........\clkdiv_20@m_to_10@m
..........\..........\.........\...................\verilog.psm
..........\..........\.........\...................\_primary.dat
..........\..........\.........\...................\_primary.dbs
..........\..........\.........\...................\_primary.vhd
..........\..........\.........\clk_by_2
..........\..........\.........\........\verilog.psm
..........\..........\.........\........\_primary.dat
..........\..........\.........\........\_primary.dbs
..........\..........\.........\........\_primary.vhd
..........\..........\.........\clk_by_2_1
..........\..........\.........\..........\verilog.psm
..........\..........\.........\..........\_primary.dat
..........\..........\.........\..........\_primary.dbs
..........\..........\.........\..........\_primary.vhd
..........\..........\.........\clk_by_2_10
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\..........\.........\...........\_primary.vhd
..........\..........\.........\clk_by_2_11
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\..........\.........\...........\_primary.vhd
..........\..........\.........\clk_by_2_12
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\..........\.........\...........\_primary.vhd
..........\..........\.........\clk_by_2_13
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\..........\.........\...........\_primary.vhd
..........\..........\.........\clk_by_2_14
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\..........\.........\...........\_primary.vhd
..........\..........\.........\clk_by_2_15
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\....
stepper_ip
..........\component
..........\constraint
..........\coreconsole
..........\designer
..........\........\impl1
..........\........\.....\designer.log
..........\........\.....\designer_genhdl.log
..........\........\.....\simulation
..........\........\.....\top_stepper_ip.adb
..........\........\.....\top_stepper_ip.dtf
..........\........\.....\..................\verify.log
..........\........\.....\top_stepper_ip.ide_des
..........\........\.....\top_stepper_ip.stp
..........\........\.....\top_stepper_ip.tcl
..........\hdl
..........\...\baud_clk_gen.v
..........\...\clkdiv_20M_to_10M.v
..........\...\clk_by_2.v
..........\...\clk_gen.v
..........\...\debounce.v
..........\...\debounce_blk.v
..........\...\divideby5.v
..........\...\div_by_16.v
..........\...\global.v
..........\...\mux_hw_sw.v
..........\...\PLL20_to_10.v
..........\...\pwm_gen_stepper.v
..........\...\recv_control.v
..........\...\serial.v
..........\...\stepper_clk_gen.v
..........\...\stepper_ip.v
..........\...\stepper_module.v
..........\...\top_serial.v
..........\...\top_stepper.v
..........\...\top_stepper_ip.v
..........\...\xmit_control.v
..........\phy_synthesis
..........\Readme_stepper_ip.txt
..........\simulation
..........\..........\modelsim.ini
..........\..........\modelsim.ini.sav
..........\..........\modelsim.log
..........\..........\postsynth
..........\..........\.........\baud_clk_gen
..........\..........\.........\............\verilog.psm
..........\..........\.........\............\_primary.dat
..........\..........\.........\............\_primary.dbs
..........\..........\.........\............\_primary.vhd
..........\..........\.........\clkdiv_20@m_to_10@m
..........\..........\.........\...................\verilog.psm
..........\..........\.........\...................\_primary.dat
..........\..........\.........\...................\_primary.dbs
..........\..........\.........\...................\_primary.vhd
..........\..........\.........\clk_by_2
..........\..........\.........\........\verilog.psm
..........\..........\.........\........\_primary.dat
..........\..........\.........\........\_primary.dbs
..........\..........\.........\........\_primary.vhd
..........\..........\.........\clk_by_2_1
..........\..........\.........\..........\verilog.psm
..........\..........\.........\..........\_primary.dat
..........\..........\.........\..........\_primary.dbs
..........\..........\.........\..........\_primary.vhd
..........\..........\.........\clk_by_2_10
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\..........\.........\...........\_primary.vhd
..........\..........\.........\clk_by_2_11
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\..........\.........\...........\_primary.vhd
..........\..........\.........\clk_by_2_12
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\..........\.........\...........\_primary.vhd
..........\..........\.........\clk_by_2_13
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\..........\.........\...........\_primary.vhd
..........\..........\.........\clk_by_2_14
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\..........\.........\...........\_primary.vhd
..........\..........\.........\clk_by_2_15
..........\..........\.........\...........\verilog.psm
..........\..........\.........\...........\_primary.dat
..........\..........\.........\...........\_primary.dbs
..........\....