压缩包 : 39709583fpga_hdl.examples.rar 列表
examples\stderr.log
examples\stdout.log
examples\synhooks_for_vif2conformal.tcl
examples\tcl\synhooks\synhooks.tcl
examples\tcl\synhooks\synhooks_for_vif2conformal.tcl
examples\tcl\tcl_find\analyze_netlist_clocks.tcl
examples\tcl\tcl_find\comb_fanout_gt_8_altera.txt
examples\tcl\tcl_find\feedthrough_altera.txt
examples\tcl\tcl_find\find_lut3_xilinx.txt
examples\tcl\tcl_find\slack_gt_2_xilinx.txt
examples\verilog\actel\prep2_2.prj
examples\verilog\actel\prep2_2.sdc
examples\verilog\altera\prep2_2.prj
examples\verilog\altera\prep2_2.sdc
examples\verilog\altera\rtl\adder8.v
examples\verilog\altera\rtl\myramv.v
examples\verilog\altera\rtl\ram64x16.v
examples\verilog\altera\rtl\sqrterr.v
examples\verilog\common_rtl\combinat\adder.v
examples\verilog\common_rtl\combinat\adder16.v
examples\verilog\common_rtl\combinat\adder8.v
examples\verilog\common_rtl\combinat\adder_8.v
examples\verilog\common_rtl\combinat\alu.v
examples\verilog\common_rtl\combinat\bitand.v
examples\verilog\common_rtl\combinat\compare.v
examples\verilog\common_rtl\combinat\decoder.v
examples\verilog\common_rtl\combinat\encoder1.v
examples\verilog\common_rtl\combinat\encoder2.v
examples\verilog\common_rtl\combinat\encoder3.v
examples\verilog\common_rtl\combinat\mux.v
examples\verilog\common_rtl\combinat\mux1.v
examples\verilog\common_rtl\combinat\mux2.v
examples\verilog\common_rtl\combinat\mux3.v
examples\verilog\common_rtl\combinat\parity.v
examples\verilog\common_rtl\combinat\sort4.v
examples\verilog\common_rtl\combinat\sqrt.v
examples\verilog\common_rtl\combinat\tristate.v
examples\verilog\common_rtl\dsp\accum.v
examples\verilog\common_rtl\dsp\addmult.v
examples\verilog\common_rtl\memory\ram_1.v
examples\verilog\common_rtl\misc\adder16.v
examples\verilog\common_rtl\misc\adder8.v
examples\verilog\common_rtl\misc\async.v
examples\verilog\common_rtl\misc\hierarcy.v
examples\verilog\common_rtl\misc\mux4to1.v
examples\verilog\common_rtl\misc\muxnew1.v
examples\verilog\common_rtl\misc\muxnew2.v
examples\verilog\common_rtl\misc\muxnew3.v
examples\verilog\common_rtl\misc\muxnew4.v
examples\verilog\common_rtl\misc\resrcshr.v
examples\verilog\common_rtl\misc\scaleabl.v
examples\verilog\common_rtl\misc\template.v
examples\verilog\common_rtl\misc\tstbench.v
examples\verilog\common_rtl\prep\prep1.v
examples\verilog\common_rtl\prep\prep1.vt
examples\verilog\common_rtl\prep\prep2.v
examples\verilog\common_rtl\prep\prep2.vt
examples\verilog\common_rtl\prep\prep2_2.v
examples\verilog\common_rtl\prep\prep3.v
examples\verilog\common_rtl\prep\prep3.vt
examples\verilog\common_rtl\prep\prep4.v
examples\verilog\common_rtl\prep\prep4.vt
examples\verilog\common_rtl\prep\prep5.v
examples\verilog\common_rtl\prep\prep5.vt
examples\verilog\common_rtl\prep\prep6.v
examples\verilog\common_rtl\prep\prep6.vt
examples\verilog\common_rtl\prep\prep7.v
examples\verilog\common_rtl\prep\prep7.vt
examples\verilog\common_rtl\prep\prep8.v
examples\verilog\common_rtl\prep\prep8.vt
examples\verilog\common_rtl\prep\prep9.v
examples\verilog\common_rtl\prep\prep9.vt
examples\verilog\common_rtl\prep\readme.txt
examples\verilog\common_rtl\sequentl\2901.v
examples\verilog\common_rtl\sequentl\counter1.v
examples\verilog\common_rtl\sequentl\counter2.v
examples\verilog\common_rtl\sequentl\dff.v
examples\verilog\common_rtl\sequentl\dff1.v
examples\verilog\common_rtl\sequentl\dff2.v
examples\verilog\common_rtl\sequentl\dff_or.v
examples\verilog\common_rtl\sequentl\latch1.v
examples\verilog\common_rtl\sequentl\latch2.v
examples\verilog\common_rtl\sequentl\latch3.v
examples\verilog\common_rtl\sequentl\latchor1.v
examples\verilog\common_rtl\sequentl\latchor2.v
examples\verilog\common_rtl\sequentl\shifter.v
examples\verilog\common_rtl\statmchs\slowl.v
examples\verilog\common_rtl\statmchs\statmch1.v
examples\verilog\common_rtl\statmchs\statmch2.v
examples\verilog\common_rtl\statmchs\statmch3.v
examples\verilog\common_rtl\statmchs\sum3.v
examples\verilog\lucent\prep2_2.prj
examples\verilog\lucent\prep2_2.sdc
examples\verilog\lucent\rtl\dff.v
examples\verilog\lucent\rtl\pad.v
examples\verilog\lucent\rtl\ram16x8.v
examples\verilog\qlogic\prep2_2.prj
examples\verilog\qlogic\prep2_2.sdc
examples\verilog\xilinx\prep2_2.prj
examples\verilog\xilinx\prep2_2.sdc
examples\verilog\xilinx\rtl\ram32x8e.v
examples\verilog\xilinx\rtl\rom16x8.v
examples\verilog\xilinx\rtl\xor9.v
examples\vhdl\actel\prep2_2.prj
examples\vhdl\actel\prep2_2.sdc
examples\vhdl\altera\prep2_2.prj
examples\vhdl\altera\prep2_2.sdc
examples\vhdl\altera\rtl\adder8.vhd
examples\vhdl\altera\rtl\eab_test.vhd
examples\vhdl\altera\rtl\lpmram.vhd
examples\vhdl\altera\rtl\myram3.vhd
examples\vhdl\common_rtl\combinat\adder.vhd
examples\vhdl\common_rtl\combinat\adder8.vhd
examples\vhdl\common_rtl\combinat\adders.vhd
examples\vhdl\common_rtl\combinat\alu.vhd
examples\vhdl\common_rtl\combinat\compare.vhd
examples\vhdl\common_rtl\combinat\decoder1.vhd
examples\vhdl\common_rtl\combinat\decoder2.vhd
examples\vhdl\common_rtl\combinat\decoder3.vhd
examples\vhdl\common_rtl\combinat\decoder4.vhd
examples\vhdl\common_rtl\combinat\encoder1.vhd
examples\vhdl\common_rtl\combinat\encoder2.vhd
examples\vhdl\common_rtl\combinat\encoder3.vhd
examples\vhdl\common_rtl\combinat\interupt.vhd
examples\vhdl\common_rtl\combinat\mux4to1.vhd
examples\vhdl\common_rtl\combinat\muxes.vhd
examples\vhdl\common_rtl\combinat\parity.vhd
examples\vhdl\common_rtl\combinat\sort4.vhd
examples\vhdl\common_rtl\combinat\tristate.vhd
examples\vhdl\common_rtl\dsp\accum.vhd
examples\vhdl\common_rtl\dsp\accum_top.vhd
examples\vhdl\common_rtl\dsp\addmult.vhd
examples\vhdl\common_rtl\dsp\addmult_top.vhd
examples\vhdl\common_rtl\memory\ram.vhd
examples\vhdl\common_rtl\misc\async.vhd
examples\vhdl\common_rtl\misc\hierarcy.vhd
examples\vhdl\common_rtl\misc\resrcshr.vhd
examples\vhdl\common_rtl\misc\scalebl1.vhd
examples\vhdl\common_rtl\misc\scalebl2.vhd
examples\vhdl\common_rtl\misc\scalebl3.vhd
examples\vhdl\common_rtl\prep\prep1.vhd
examples\vhdl\common_rtl\prep\prep1.vht
examples\vhdl\common_rtl\prep\prep2.vhd
examples\vhdl\common_rtl\prep\prep2.vht
examples\vhdl\common_rtl\prep\prep2_2.vhd
examples\vhdl\common_rtl\prep\prep3.vhd
examples\vhdl\common_rtl\prep\prep3.vht
examples\vhdl\common_rtl\prep\prep4.vhd
examples\vhdl\common_rtl\prep\prep4.vht
examples\vhdl\common_rtl\prep\prep5.vhd
examples\vhdl\common_rtl\prep\prep5.vht
examples\vhdl\common_rtl\prep\prep6.vhd
examples\vhdl\common_rtl\prep\prep6.vht
examples\vhdl\common_rtl\prep\prep7.vhd
examples\vhdl\common_rtl\prep\prep7.vht
examples\vhdl\common_rtl\prep\prep8.vhd
examples\vhdl\common_rtl\prep\prep8.vht
examples\vhdl\common_rtl\prep\prep9.vhd
examples\vhdl\common_rtl\prep\prep9.vht
examples\vhdl\common_rtl\sequentl\2901.vhd
examples\vhdl\common_rtl\sequentl\2901_2d.vhd
examples\vhdl\common_rtl\sequentl\counter1.vhd
examples\vhdl\common_rtl\sequentl\counter2.vhd
examples\vhdl\common_rtl\sequentl\counter3.vhd
examples\vhdl\common_rtl\sequentl\counter4.vhd
examples\vhdl\common_rtl\sequentl\counter5.vhd
examples\vhdl\common_rtl\sequentl\dff1.vhd
examples\vhdl\common_rtl\sequentl\dff2.vhd
examples\vhdl\common_rtl\sequentl\dff_ors.vhd
examples\vhdl\common_rtl\sequentl\latches.vhd
examples\vhdl\common_rtl\sequentl\latches2.vhd
examples\vhdl\common_rtl\sequentl\latchor1.vhd
examples\vhdl\common_rtl\sequentl\latchor2.vhd
examples\vhdl\common_rtl\sequentl\mistake.vhd
examples\vhdl\common_rtl\sequentl\regfile.vhd
examples\vhdl\common_rtl\sequentl\shifter.vhd
examples\vhdl\common_rtl\statmchs\implicit.vhd
examples\vhdl\common_rtl\statmchs\statmch1.vhd
examples\vhdl\common_rtl\statmchs\statmch2.vhd
examples\vhdl\lucent\prep2_2.prj
examples\vhdl\lucent\prep2_2.sdc
examples\vhdl\lucent\rtl\pad.vhd
examples\vhdl\lucent\rtl\ram16x8.vhd
examples\vhdl\qlogic\prep2_2.prj
examples\vhdl\qlogic\prep2_2.sdc
examples\vhdl\xilinx\prep2_2.prj
examples\vhdl\xilinx\prep2_2.sdc
examples\vhdl\xilinx\rtl\ram32x8e.vhd
examples\vhdl\xilinx\rtl\rom16x8.vhd
examples\verilog\altera\rtl
examples\verilog\common_rtl\combinat
examples\verilog\common_rtl\dsp
examples\verilog\common_rtl\memory
examples\verilog\common_rtl\misc
examples\verilog\common_rtl\prep
examples\verilog\common_rtl\sequentl
examples\verilog\common_rtl\statmchs
examples\verilog\lucent\rtl
examples\verilog\xilinx\rtl
examples\vhdl\altera\rtl
examples\vhdl\common_rtl\combinat
examples\vhdl\common_rtl\dsp
examples\vhdl\common_rtl\memory
examples\vhdl\common_rtl\misc
examples\vhdl\common_rtl\prep
examples\vhdl\common_rtl\sequentl
examples\vhdl\common_rtl\statmchs
examples\vhdl\lucent\rtl
examples\vhdl\xilinx\rtl
examples\tcl\synhooks
examples\tcl\tcl_find
examples\verilog\actel
examples\verilog\altera
examples\verilog\common_rtl
examples\verilog\lucent
examples\verilog\qlogic
examples\verilog\xilinx
examples\vhdl\actel
examples\vhdl\altera
examples\vhdl\common_rtl
examples\vhdl\lucent
examples\vhdl\qlogic
examples\vhdl\xilinx
examples\tcl
examples\utilities
examples\verilog
examples\vhdl
examples