文件名称:an486_design_example
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VHDL实现SPI接口转I2c接口的源代码，可以直接调用
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压缩包 : 3971002an486_design_example.rar 列表 an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\code\SPI_to_I2C.v an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\SPI_to_I2C.cr.mti an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\SPI_to_I2C.mpf an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\SPI_to_I2C.v an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\SPI_to_I2C_test.v an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\SPI_to_I2C_test.v.bak an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\transcript an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\vsim.wlf an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.bmp an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.do an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@i2@c_master\verilog.psm an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@i2@c_master\_primary.dat an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@i2@c_master\_primary.vhd an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_slave\verilog.psm an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_slave\_primary.dat an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_slave\_primary.vhd an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c\verilog.psm an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c\_primary.dat an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c\_primary.vhd an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c_test\verilog.psm an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c_test\_primary.dat an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c_test\_primary.vhd an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\divider\verilog.psm an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\divider\_primary.dat an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\divider\_primary.vhd an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\internal_oss_altufm_osc_7p3\verilog.psm an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\internal_oss_altufm_osc_7p3\_primary.dat an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\internal_oss_altufm_osc_7p3\_primary.vhd an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\_info an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.(0).cnf.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.(0).cnf.hdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.(1).cnf.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.(1).cnf.hdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.(2).cnf.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.(2).cnf.hdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.(3).cnf.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.(3).cnf.hdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.(4).cnf.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.(4).cnf.hdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.asm.qmsg an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.asm_labs.ddb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cbx.xml an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp.hdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp.logdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp.rdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp.tdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.cmp0.ddb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.dbp an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.db_info an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.fit.qmsg an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.hier_info an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.hif an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.map.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.map.hdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.map.logdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.map.qmsg an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.pre_map.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.pre_map.hdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.psp an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.pss an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.rtlv.hdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.rtlv_sg.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.rtlv_sg_swap.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.sgdiff.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.sgdiff.hdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.signalprobe.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.sld_design_entry_dsc.sci an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.syn_hier_info an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.tan.qmsg an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.tis_db_list.ddb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.sld_design_entry.sci an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db\SPI_to_I2C.eco.cdb an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.asm.rpt an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.done an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.dpf an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.fit.rpt an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.fit.smsg an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.fit.summary an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.flow.rpt an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.map.rpt an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.map.smsg an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.map.summary an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.pin an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.pof an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.qarlog an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.qpf an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.qsf an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.tan.rpt an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.tan.summary an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.v an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C_assignment_defaults.qdf an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\SPI_to_I2C.qws an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\testbench\SPI_to_I2C_test.v an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@i2@c_master an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_slave an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\@s@p@i_to_@i2@c_test an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\divider an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work\internal_oss_altufm_osc_7p3 an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim\work an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus\db an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\code an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\modelsim an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\quartus an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example\testbench an486_design_example\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example an486_design_example