压缩包 : 81404568verilog.rar 列表
Models and Testbenches 11_10_2004\README.txt
Models and Testbenches 11_10_2004\_vti_cnf\Models and Testbenches 05_10_2004.rar
Models and Testbenches 11_10_2004\_vti_cnf\Models and Testbenches 05_10_2004.zip
Models and Testbenches 11_10_2004\_vti_cnf\Models and Testbenches10_6_04.zip
Models and Testbenches 11_10_2004\_vti_cnf
Models and Testbenches 11_10_2004\Clock generator\clock.v
Models and Testbenches 11_10_2004\Clock generator\clock_1_2.v
Models and Testbenches 11_10_2004\Clock generator\clock_gen.v
Models and Testbenches 11_10_2004\Clock generator\Clock_Prog.v
Models and Testbenches 11_10_2004\Clock generator\Clock_Unit.v
Models and Testbenches 11_10_2004\Clock generator
Models and Testbenches 11_10_2004\Chapter 9\ADDVB_Models_9.doc
Models and Testbenches 11_10_2004\Chapter 9\_vti_cnf\ADDVB_Models_9.doc
Models and Testbenches 11_10_2004\Chapter 9\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\Image_Converter_0.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\Image_Converter_1.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\Image_converter_2.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\Image_Converter_Baseline.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\t_Image_Converter_0.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\t_Image_Converter_1.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\t_Image_Converter_2.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\t_Image_Converter_Baseline.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\_vti_cnf\Image_Converter_0.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\_vti_cnf\Image_Converter_1.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\_vti_cnf\Image_converter_2.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\_vti_cnf\Image_Converter_Baseline.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\_vti_cnf\t_Image_Converter_0.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\_vti_cnf\t_Image_Converter_1.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\_vti_cnf\t_Image_Converter_2.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\_vti_cnf\t_Image_Converter_Baseline.v
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 9\Pixel Converter
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\Circular_Buffer_1.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\Circular_Buffer_2.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\FIFO_Buffer.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\Ser_Par_Conv_32.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\Ser_Par_Conv_8.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\t_Circular_Buffers.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\t_FIFO_Buffer.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\t_FIFO_Clock_Domain_Synch.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\t_Ser_Par_Conv_32.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\t_Ser_Par_Conv_8.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\t_write_synch.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\write_synch.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\Circular_Buffer_1.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\Circular_Buffer_2.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\FIFO_Buffer.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\Ser_Par_Conv_32.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\Ser_Par_Conv_8.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\t_Circular_Buffers.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\t_FIFO_Buffer.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\t_FIFO_Clock_Domain_Synch.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\t_Ser_Par_Conv_32.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\t_Ser_Par_Conv_8.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\t_write_synch.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf\write_synch.v
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 9\Pipeline and FIFO
Models and Testbenches 11_10_2004\Chapter 9\DSP\decimator_1.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\decimator_2.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\decimator_3.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\FIR_Gaussian.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\IIR_Filter.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\integrator_par.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\Integrator_Seq.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\test_FIR_Gaussian.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\test_IIR.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\t_decimator_1.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\t_decimator_2.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\t_decimator_3.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\t_integrator_par.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\t_Integrator_Seq.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\decimator_1.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\decimator_2.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\decimator_3.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\FIR_Gaussian.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\IIR_Filter.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\integrator_par.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\Integrator_Seq.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\test_FIR_Gaussian.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\test_IIR.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\t_decimator_1.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\t_decimator_2.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\t_decimator_3.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\t_integrator_par.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf\t_Integrator_Seq.v
Models and Testbenches 11_10_2004\Chapter 9\DSP\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 9\DSP
Models and Testbenches 11_10_2004\Chapter 9\Bubble Sorter\Bubble_sort.v
Models and Testbenches 11_10_2004\Chapter 9\Bubble Sorter\_vti_cnf\Bubble_sort.v
Models and Testbenches 11_10_2004\Chapter 9\Bubble Sorter\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 9\Bubble Sorter
Models and Testbenches 11_10_2004\Chapter 9
Models and Testbenches 11_10_2004\Chapter 8\ADDVB_Models_8.doc
Models and Testbenches 11_10_2004\Chapter 8\BCD_to_Excess_3_ROM.v
Models and Testbenches 11_10_2004\Chapter 8\Counter8_prog.v
Models and Testbenches 11_10_2004\Chapter 8\FIFO.v
Models and Testbenches 11_10_2004\Chapter 8\PLA_array.v
Models and Testbenches 11_10_2004\Chapter 8\PLA_plane.v
Models and Testbenches 11_10_2004\Chapter 8\RAM_2048_8.v
Models and Testbenches 11_10_2004\Chapter 8\RAM_static.v
Models and Testbenches 11_10_2004\Chapter 8\RAM_static_BD.v
Models and Testbenches 11_10_2004\Chapter 8\Row_Signal.v
Models and Testbenches 11_10_2004\Chapter 8\SRAM_with_Con.v
Models and Testbenches 11_10_2004\Chapter 8\top_keypad_FIFO.v
Models and Testbenches 11_10_2004\Chapter 8\t_keypad_FIFO.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\ADDVB_Models_8.doc
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\BCD_to_Excess_3_ROM.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\Counter8_prog.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\FIFO.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\PLA_array.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\PLA_plane.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\RAM_2048_8.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\RAM_static.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\RAM_static_BD.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\Row_Signal.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\SRAM_with_Con.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\top_keypad_FIFO.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf\t_keypad_FIFO.v
Models and Testbenches 11_10_2004\Chapter 8\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 8
Models and Testbenches 11_10_2004\Chapter 7\ADDVB_Models_7.doc
Models and Testbenches 11_10_2004\Chapter 7\ADDVB_Models_7.v.txt
Models and Testbenches 11_10_2004\Chapter 7\Bin_Cnt_Part_RTL.v
Models and Testbenches 11_10_2004\Chapter 7\Bin_Cnt_Part_RTL_by_3.v
Models and Testbenches 11_10_2004\Chapter 7\Clock_Unit.v
Models and Testbenches 11_10_2004\Chapter 7\Gap_Finder.doc
Models and Testbenches 11_10_2004\Chapter 7\Gap_Finder.v
Models and Testbenches 11_10_2004\Chapter 7\RISC_SPM.v
Models and Testbenches 11_10_2004\Chapter 7\test_RISC_SPM.v
Models and Testbenches 11_10_2004\Chapter 7\t_Bin_Cnt_Part_RTL_by_3.v
Models and Testbenches 11_10_2004\Chapter 7\uart8_rcvr.v
Models and Testbenches 11_10_2004\Chapter 7\uart8_rcvr_partition.v
Models and Testbenches 11_10_2004\Chapter 7\UART_xmtr_Arch.v
Models and Testbenches 11_10_2004\Chapter 7\~$DVB_Models_7.doc
Models and Testbenches 11_10_2004\Chapter 7\_vti_cnf\ADDVB_Models_7.doc
Models and Testbenches 11_10_2004\Chapter 7\_vti_cnf\Bin_Cnt_Part_RTL.v
Models and Testbenches 11_10_2004\Chapter 7\_vti_cnf\Bin_Cnt_Part_RTL_by_3.v
Models and Testbenches 11_10_2004\Chapter 7\_vti_cnf\RISC_SPM.v
Models and Testbenches 11_10_2004\Chapter 7\_vti_cnf\test_RISC_SPM.v
Models and Testbenches 11_10_2004\Chapter 7\_vti_cnf\t_Bin_Cnt_Part_RTL_by_3.v
Models and Testbenches 11_10_2004\Chapter 7\_vti_cnf\uart8_rcvr.v
Models and Testbenches 11_10_2004\Chapter 7\_vti_cnf\uart8_rcvr_partition.v
Models and Testbenches 11_10_2004\Chapter 7\_vti_cnf\UART_xmtr_Arch.v
Models and Testbenches 11_10_2004\Chapter 7\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 7
Models and Testbenches 11_10_2004\Chapter 6\ADDVB_Models_6.doc
Models and Testbenches 11_10_2004\Chapter 6\Add_Accum_1.v
Models and Testbenches 11_10_2004\Chapter 6\Add_Accum_2.v
Models and Testbenches 11_10_2004\Chapter 6\Add_Accum_both.v
Models and Testbenches 11_10_2004\Chapter 6\alu_with_z1.v
Models and Testbenches 11_10_2004\Chapter 6\badd_4.v
Models and Testbenches 11_10_2004\Chapter 6\BCD_to_Excess_3a.v
Models and Testbenches 11_10_2004\Chapter 6\BCD_to_Excess_3b.v
Models and Testbenches 11_10_2004\Chapter 6\BCD_to_Excess_3b_Post.v
Models and Testbenches 11_10_2004\Chapter 6\BCD_to_Excess_3c.v
Models and Testbenches 11_10_2004\Chapter 6\BCD_to_Excess_3c_Post.v
Models and Testbenches 11_10_2004\Chapter 6\Bi_dir_bus.v
Models and Testbenches 11_10_2004\Chapter 6\boole_opt.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_a.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_b.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_b0.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_b1.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_b2.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_c.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_d.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_IMP.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_SD.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_SD_0.v
Models and Testbenches 11_10_2004\Chapter 6\count_ones_SM.v
Models and Testbenches 11_10_2004\Chapter 6\D_reg4_a.v
Models and Testbenches 11_10_2004\Chapter 6\expression_sub.v
Models and Testbenches 11_10_2004\Chapter 6\expression_sub_nb.v
Models and Testbenches 11_10_2004\Chapter 6\for_and_loop_comb.v
Models and Testbenches 11_10_2004\Chapter 6\Latched_Seven_Seg_Display.v
Models and Testbenches 11_10_2004\Chapter 6\latch_if1.v
Models and Testbenches 11_10_2004\Chapter 6\latch_if2.v
Models and Testbenches 11_10_2004\Chapter 6\multiple_reg_assign.v
Models and Testbenches 11_10_2004\Chapter 6\mux_4pri.v
Models and Testbenches 11_10_2004\Chapter 6\mux_latch.v
Models and Testbenches 11_10_2004\Chapter 6\mux_logic.v
Models and Testbenches 11_10_2004\Chapter 6\mux_reg.v
Models and Testbenches 11_10_2004\Chapter 6\NRZI.v
Models and Testbenches 11_10_2004\Chapter 6\NRZ_2_Manchester_Mealy.v
Models and Testbenches 11_10_2004\Chapter 6\NRZ_2_Manchester_Mealy_Post.v
Models and Testbenches 11_10_2004\Chapter 6\NRZ_2_Manchester_Moore.v
Models and Testbenches 11_10_2004\Chapter 6\NRZ_2_Manchester_Moore_Post.v
Models and Testbenches 11_10_2004\Chapter 6\operator_group.v
Models and Testbenches 11_10_2004\Chapter 6\or4_behav.v
Models and Testbenches 11_10_2004\Chapter 6\or4_behav_latch.v
Models and Testbenches 11_10_2004\Chapter 6\or_nand.v
Models and Testbenches 11_10_2004\Chapter 6\res_share.v
Models and Testbenches 11_10_2004\Chapter 6\ripple_counter.v
Models and Testbenches 11_10_2004\Chapter 6\Seq_Rec_3_1s.v
Models and Testbenches 11_10_2004\Chapter 6\Seq_Rec_3_1s_Mealy.v
Models and Testbenches 11_10_2004\Chapter 6\Seq_Rec_3_1s_Moore.v
Models and Testbenches 11_10_2004\Chapter 6\Seq_Rec_3_1s_Shft_Reg.v
Models and Testbenches 11_10_2004\Chapter 6\Seq_Rec_Moore_imp.v
Models and Testbenches 11_10_2004\Chapter 6\shifter_1.v
Models and Testbenches 11_10_2004\Chapter 6\shifter_2.v
Models and Testbenches 11_10_2004\Chapter 6\swap_synch.v
Models and Testbenches 11_10_2004\Chapter 6\Test_count_ones_a.v
Models and Testbenches 11_10_2004\Chapter 6\Test_count_ones_b.v
Models and Testbenches 11_10_2004\Chapter 6\Test_count_ones_c.v
Models and Testbenches 11_10_2004\Chapter 6\Test_count_ones_d.v
Models and Testbenches 11_10_2004\Chapter 6\Test_count_ones_IMP.v
Models and Testbenches 11_10_2004\Chapter 6\Test_count_ones_SD.v
Models and Testbenches 11_10_2004\Chapter 6\Test_count_ones_SD_0.v
Models and Testbenches 11_10_2004\Chapter 6\Test_count_ones_SM.v
Models and Testbenches 11_10_2004\Chapter 6\test_NRZ_2_Manchester_Moore.v
Models and Testbenches 11_10_2004\Chapter 6\Test_Seq_Rec_Moore_imp.v
Models and Testbenches 11_10_2004\Chapter 6\t_BCD_Excess_3.v
Models and Testbenches 11_10_2004\Chapter 6\Uni_dir_bus.v.doc
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\ADDVB_Models_6.doc
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Add_Accum_1.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Add_Accum_2.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Add_Accum_both.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\alu_with_z1.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\badd_4.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\BCD_to_Excess_3a.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\BCD_to_Excess_3b.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\BCD_to_Excess_3b_Post.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\BCD_to_Excess_3c.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\BCD_to_Excess_3c_Post.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Bi_dir_bus.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\boole_opt.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\count_ones_a.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\count_ones_b.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\count_ones_b0.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\count_ones_b1.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\count_ones_b2.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\count_ones_c.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\count_ones_d.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\count_ones_IMP.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\count_ones_SD.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\count_ones_SM.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\D_reg4_a.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\expression_sub.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\expression_sub_nb.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\for_and_loop_comb.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Latched_Seven_Seg_Display.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\latch_if1.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\latch_if2.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\multiple_reg_assign.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\mux_4pri.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\mux_latch.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\mux_logic.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\mux_reg.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\NRZI.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\NRZ_2_Manchester_Mealy.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\NRZ_2_Manchester_Mealy_Post.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\NRZ_2_Manchester_Moore.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\NRZ_2_Manchester_Moore_Post.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\operator_group.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\or4_behav.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\or4_behav_latch.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\or_nand.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\res_share.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\ripple_counter.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Seq_Rec_3_1s.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Seq_Rec_3_1s_Mealy.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Seq_Rec_3_1s_Moore.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Seq_Rec_3_1s_Shft_Reg.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Seq_Rec_Moore_imp.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\shifter_1.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\shifter_2.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\swap_synch.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Test_count_ones_a.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Test_count_ones_b.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Test_count_ones_c.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Test_count_ones_d.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Test_count_ones_IMP.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Test_count_ones_SD.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Test_count_ones_SM.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\test_NRZ_2_Manchester_Moore.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Test_Seq_Rec_Moore_imp.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\t_BCD_Excess_3.v
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf\Uni_dir_bus.v.doc
Models and Testbenches 11_10_2004\Chapter 6\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 6
Models and Testbenches 11_10_2004\Chapter 5\adder_task.v
Models and Testbenches 11_10_2004\Chapter 5\ADDVB_Models_5.doc
Models and Testbenches 11_10_2004\Chapter 5\add_4cycle.v
Models and Testbenches 11_10_2004\Chapter 5\AOI_5_CA0.v
Models and Testbenches 11_10_2004\Chapter 5\AOI_5_CA1.v
Models and Testbenches 11_10_2004\Chapter 5\AOI_5_CA2.v
Models and Testbenches 11_10_2004\Chapter 5\AOI_5_CA3.v
Models and Testbenches 11_10_2004\Chapter 5\arithmetic_unit.v
Models and Testbenches 11_10_2004\Chapter 5\asynch_df_behav.v
Models and Testbenches 11_10_2004\Chapter 5\Auto_LFSR_ALGO.v
Models and Testbenches 11_10_2004\Chapter 5\Auto_LFSR_Param.v
Models and Testbenches 11_10_2004\Chapter 5\Auto_LFSR_RTL.v
Models and Testbenches 11_10_2004\Chapter 5\barrel_shifter.v
Models and Testbenches 11_10_2004\Chapter 5\comparator.v
Models and Testbenches 11_10_2004\Chapter 5\compare_2_algo.v
Models and Testbenches 11_10_2004\Chapter 5\compare_2_CA0.v
Models and Testbenches 11_10_2004\Chapter 5\compare_2_CA1.txt
Models and Testbenches 11_10_2004\Chapter 5\compare_2_CA1.v
Models and Testbenches 11_10_2004\Chapter 5\compare_2_ROM.v
Models and Testbenches 11_10_2004\Chapter 5\compare_2_RTL.v
Models and Testbenches 11_10_2004\Chapter 5\compare_32_CA.v
Models and Testbenches 11_10_2004\Chapter 5\decoder.v
Models and Testbenches 11_10_2004\Chapter 5\df_behav.v
Models and Testbenches 11_10_2004\Chapter 5\encoder.v
Models and Testbenches 11_10_2004\Chapter 5\find_first_one.v
Models and Testbenches 11_10_2004\Chapter 5\Hex_Keypad_Grayhill_072.v
Models and Testbenches 11_10_2004\Chapter 5\Latch_CA.v
Models and Testbenches 11_10_2004\Chapter 5\Latch_Rbar_CA.v
Models and Testbenches 11_10_2004\Chapter 5\Majority.v
Models and Testbenches 11_10_2004\Chapter 5\Majority_4b.v
Models and Testbenches 11_10_2004\Chapter 5\Mux_4_32_CA.v
Models and Testbenches 11_10_2004\Chapter 5\Mux_4_32_case.v
Models and Testbenches 11_10_2004\Chapter 5\Mux_4_32_if.v
Models and Testbenches 11_10_2004\Chapter 5\Par_load_reg4.v
Models and Testbenches 11_10_2004\Chapter 5\pipe_2stage.v
Models and Testbenches 11_10_2004\Chapter 5\priority.v
Models and Testbenches 11_10_2004\Chapter 5\Register_File.v
Models and Testbenches 11_10_2004\Chapter 5\ring_counter.v
Models and Testbenches 11_10_2004\Chapter 5\Row_Signal.v
Models and Testbenches 11_10_2004\Chapter 5\Seven_Seg_Display.v
Models and Testbenches 11_10_2004\Chapter 5\shiftreg_nb.v
Models and Testbenches 11_10_2004\Chapter 5\shiftreg_PA.v
Models and Testbenches 11_10_2004\Chapter 5\shiftreg_PA_rev.v
Models and Testbenches 11_10_2004\Chapter 5\Shift_reg4.v
Models and Testbenches 11_10_2004\Chapter 5\shift_reg_PA.v
Models and Testbenches 11_10_2004\Chapter 5\Synchronizer.v
Models and Testbenches 11_10_2004\Chapter 5\synchro_2.v
Models and Testbenches 11_10_2004\Chapter 5\tr_latch.v
Models and Testbenches 11_10_2004\Chapter 5\t_AOI_5_CA1.v
Models and Testbenches 11_10_2004\Chapter 5\t_AOI_5_CA2.v
Models and Testbenches 11_10_2004\Chapter 5\t_Bin_Cnt_Part_RTL.v
Models and Testbenches 11_10_2004\Chapter 5\t_Hex_Keypad_Grayhill_072.v
Models and Testbenches 11_10_2004\Chapter 5\t_Latch_CA.v
Models and Testbenches 11_10_2004\Chapter 5\t_Latch_Rbar_CA.v
Models and Testbenches 11_10_2004\Chapter 5\Universal_Shift_Reg.v
Models and Testbenches 11_10_2004\Chapter 5\Universal_Shift_Register.v
Models and Testbenches 11_10_2004\Chapter 5\up_down_counter.v
Models and Testbenches 11_10_2004\Chapter 5\Up_Down_Implicit1.v
Models and Testbenches 11_10_2004\Chapter 5\word_aligner.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\adder_task.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\ADDVB_Models_5.doc
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\add_4cycle.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\AOI_5_CA0.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\AOI_5_CA1.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\AOI_5_CA2.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\AOI_5_CA3.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\arithmetic_unit.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\asynch_df_behav.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Auto_LFSR_ALGO.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Auto_LFSR_Param.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Auto_LFSR_RTL.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\barrel_shifter.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\comparator.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\compare_2_algo.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\compare_2_CA0.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\compare_2_CA1.txt
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\compare_2_CA1.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\compare_2_ROM.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\compare_2_RTL.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\compare_32_CA.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\decoder.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\df_behav.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\encoder.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\find_first_one.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Hex_Keypad_Grayhill_072.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Latch_CA.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Latch_Rbar_CA.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Majority.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Majority_4b.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Mux_4_32_CA.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Mux_4_32_case.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Mux_4_32_if.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Par_load_reg4.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\pipe_2stage.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\priority.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Register_File.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\ring_counter.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Row_Signal.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Seven_Seg_Display.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\shiftreg_nb.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\shiftreg_PA.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\shiftreg_PA_rev.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Shift_reg4.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\shift_reg_PA.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Synchronizer.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\synchro_2.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\tr_latch.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\t_AOI_5_CA1.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\t_AOI_5_CA2.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\t_Bin_Cnt_Part_RTL.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\t_Hex_Keypad_Grayhill_072.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\t_Latch_CA.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\t_Latch_Rbar_CA.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Universal_Shift_Reg.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Universal_Shift_Register.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\up_down_counter.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\Up_Down_Implicit1.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf\word_aligner.v
Models and Testbenches 11_10_2004\Chapter 5\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 5
Models and Testbenches 11_10_2004\Chapter 4\ADDVB_Models_4.doc
Models and Testbenches 11_10_2004\Chapter 4\Add_rca_4.v
Models and Testbenches 11_10_2004\Chapter 4\AOI_str.v
Models and Testbenches 11_10_2004\Chapter 4\AOI_UDP.v
Models and Testbenches 11_10_2004\Chapter 4\compare_2_str.v
Models and Testbenches 11_10_2004\Chapter 4\compare_4_str.v
Models and Testbenches 11_10_2004\Chapter 4\Mux_2_32_CA.v
Models and Testbenches 11_10_2004\Chapter 4\Mux_4_32_CA.v
Models and Testbenches 11_10_2004\Chapter 4\Mux_4_32_case.v
Models and Testbenches 11_10_2004\Chapter 4\Mux_4_32_CA_if.v
Models and Testbenches 11_10_2004\Chapter 4\test_hiZ.v
Models and Testbenches 11_10_2004\Chapter 4\t_Add_full_ASIC.v
Models and Testbenches 11_10_2004\Chapter 4\t_Add_full_unit_delay.v
Models and Testbenches 11_10_2004\Chapter 4\t_Add_half.v
Models and Testbenches 11_10_2004\Chapter 4\t_Add_rca_4_Unit_Delay.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\ADDVB_Models_4.doc
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\Add_rca_4.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\AOI_str.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\AOI_UDP.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\compare_2_str.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\compare_4_str.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\Mux_2_32_CA.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\Mux_4_32_CA.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\Mux_4_32_case.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\Mux_4_32_CA_if.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\test_hiZ.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\t_Add_full_ASIC.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\t_Add_full_unit_delay.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\t_Add_half.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf\t_Add_rca_4_Unit_Delay.v
Models and Testbenches 11_10_2004\Chapter 4\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 4
Models and Testbenches 11_10_2004\Chapter 11\ADDVB_Models_11.doc
Models and Testbenches 11_10_2004\Chapter 11\Latch_Races.v
Models and Testbenches 11_10_2004\Chapter 11\_vti_cnf\ADDVB_Models_11.doc
Models and Testbenches 11_10_2004\Chapter 11\_vti_cnf\Latch_Races.v
Models and Testbenches 11_10_2004\Chapter 11\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 11\JTAG\ASIC_with_TAP.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\Boundary_Scan_Register.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\BR_Cell.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\BSC_Cell.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\Instruction_Decoder.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\Instruction_Register.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\IR_Cell.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\tap_controller.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\TAP_FSM.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\TDI_Generator.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\TDO_Monitor.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\t_ASIC_with_TAP.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\t_Boundary_Scan_Register.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\t_Instruction_Register.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\ASIC_with_TAP.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\Boundary_Scan_Register.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\BR_Cell.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\BSC_Cell.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\Instruction_Decoder.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\Instruction_Register.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\IR_Cell.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\tap_controller.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\TAP_FSM.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\TDI_Generator.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\TDO_Monitor.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\t_ASIC_with_TAP.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\t_Boundary_Scan_Register.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf\t_Instruction_Register.v
Models and Testbenches 11_10_2004\Chapter 11\JTAG\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 11\JTAG
Models and Testbenches 11_10_2004\Chapter 11\BIST\ASIC_with_BIST.v
Models and Testbenches 11_10_2004\Chapter 11\BIST\t_ASIC_with_BIST.v
Models and Testbenches 11_10_2004\Chapter 11\BIST\_vti_cnf\ASIC_with_BIST.v
Models and Testbenches 11_10_2004\Chapter 11\BIST\_vti_cnf\t_ASIC_with_BIST.v
Models and Testbenches 11_10_2004\Chapter 11\BIST\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 11\BIST
Models and Testbenches 11_10_2004\Chapter 11
Models and Testbenches 11_10_2004\Chapter 10\ADDVB_Models_10.doc
Models and Testbenches 11_10_2004\Chapter 10\_vti_cnf\ADDVB_Models_10.doc
Models and Testbenches 11_10_2004\Chapter 10\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\Multiplier_ASM_0.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\Multiplier_ASM_1.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\Multiplier_Booth_STG_0.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\Multiplier_Implicit_1.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\Multiplier_Implicit_2.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\Multiplier_RR_ASM.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\Multiplier_STG_0.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\Multiplier_STG_1.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\Radix_4__STG_0.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\_vti_cnf\Multiplier_ASM_0.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\_vti_cnf\Multiplier_ASM_1.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\_vti_cnf\Multiplier_Booth_STG_0.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\_vti_cnf\Multiplier_Implicit_1.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\_vti_cnf\Multiplier_Implicit_2.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\_vti_cnf\Multiplier_RR_ASM.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\_vti_cnf\Multiplier_STG_0.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\_vti_cnf\Multiplier_STG_1.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\_vti_cnf\Radix_4__STG_0.v
Models and Testbenches 11_10_2004\Chapter 10\Multipliers\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 10\Multipliers
Models and Testbenches 11_10_2004\Chapter 10\Dividers\Divider_RR_STG.v
Models and Testbenches 11_10_2004\Chapter 10\Dividers\Divider_STG_0.v
Models and Testbenches 11_10_2004\Chapter 10\Dividers\Divider_STG_0_sub.v
Models and Testbenches 11_10_2004\Chapter 10\Dividers\Divider_STG_1.v
Models and Testbenches 11_10_2004\Chapter 10\Dividers\t_Divider_RR_STG.v
Models and Testbenches 11_10_2004\Chapter 10\Dividers\_vti_cnf\Divider_RR_STG.v
Models and Testbenches 11_10_2004\Chapter 10\Dividers\_vti_cnf\Divider_STG_0.v
Models and Testbenches 11_10_2004\Chapter 10\Dividers\_vti_cnf\Divider_STG_0_sub.v
Models and Testbenches 11_10_2004\Chapter 10\Dividers\_vti_cnf\Divider_STG_1.v
Models and Testbenches 11_10_2004\Chapter 10\Dividers\_vti_cnf\t_Divider_RR_STG.v
Models and Testbenches 11_10_2004\Chapter 10\Dividers\_vti_cnf
Models and Testbenches 11_10_2004\Chapter 10\Dividers
Models and Testbenches 11_10_2004\Chapter 10
Models and Testbenches 11_10_2004