文件名称:pci_core_verilog
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PCI-master的核，verilog语言，经测试，可完成芯片的综合及布线
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下载文件列表
压缩包 : 109201286pci_core_verilog.rar 列表 rtl\' rtl\bus_commands.v rtl\pci_async_reset_flop(1).v rtl\pci_async_reset_flop.v rtl\pci_bridge32(1).v rtl\pci_bridge32.v rtl\pci_cbe_en_crit(1).v rtl\pci_cbe_en_crit.v rtl\pci_conf_cyc_addr_dec(1).v rtl\pci_conf_cyc_addr_dec.v rtl\pci_conf_space(1).v rtl\pci_conf_space.v rtl\pci_constants(1).v rtl\pci_constants.v rtl\pci_cur_out_reg(1).v rtl\pci_cur_out_reg.v rtl\pci_delayed_sync(1).v rtl\pci_delayed_sync.v rtl\pci_delayed_write_reg(1).v rtl\pci_delayed_write_reg.v rtl\pci_frame_crit(1).v rtl\pci_frame_crit.v rtl\pci_frame_en_crit.v rtl\pci_wbr_fifo_control(1).v rtl\pci_wbr_fifo_control.v rtl\pci_wbs_wbb3_2_wbb2(1).v rtl\pci_wbs_wbb3_2_wbb2.v rtl\pci_wbw_fifo_control(1).v rtl\pci_wbw_fifo_control.v rtl\pci_wbw_wbr_fifos(1).v rtl\pci_wbw_wbr_fifos.v rtl\pci_wb_tpram.v rtl\timescale(1).v rtl\timescale.v rtl