文件名称:pci_core_verilog
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PCI-master的核，verilog语言，经测试，可完成芯片的综合及布线-PCI-master s nuclear, verilog language, by testing, to be completed by the integrated chip and wiring
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...\'
...\bus_commands.v
...\pci_async_reset_flop(1).v
...\pci_async_reset_flop.v
...\pci_bridge32(1).v
...\pci_bridge32.v
...\pci_cbe_en_crit(1).v
...\pci_cbe_en_crit.v
...\pci_conf_cyc_addr_dec(1).v
...\pci_conf_cyc_addr_dec.v
...\pci_conf_space(1).v
...\pci_conf_space.v
...\pci_constants(1).v
...\pci_constants.v
...\pci_cur_out_reg(1).v
...\pci_cur_out_reg.v
...\pci_delayed_sync(1).v
...\pci_delayed_sync.v
...\pci_delayed_write_reg(1).v
...\pci_delayed_write_reg.v
...\pci_frame_crit(1).v
...\pci_frame_crit.v
...\pci_frame_en_crit.v
...\pci_wbr_fifo_control(1).v
...\pci_wbr_fifo_control.v
...\pci_wbs_wbb3_2_wbb2(1).v
...\pci_wbs_wbb3_2_wbb2.v
...\pci_wbw_fifo_control(1).v
...\pci_wbw_fifo_control.v
...\pci_wbw_wbr_fifos(1).v
...\pci_wbw_wbr_fifos.v
...\pci_wb_tpram.v
...\timescale(1).v
...\timescale.v
...\'
...\bus_commands.v
...\pci_async_reset_flop(1).v
...\pci_async_reset_flop.v
...\pci_bridge32(1).v
...\pci_bridge32.v
...\pci_cbe_en_crit(1).v
...\pci_cbe_en_crit.v
...\pci_conf_cyc_addr_dec(1).v
...\pci_conf_cyc_addr_dec.v
...\pci_conf_space(1).v
...\pci_conf_space.v
...\pci_constants(1).v
...\pci_constants.v
...\pci_cur_out_reg(1).v
...\pci_cur_out_reg.v
...\pci_delayed_sync(1).v
...\pci_delayed_sync.v
...\pci_delayed_write_reg(1).v
...\pci_delayed_write_reg.v
...\pci_frame_crit(1).v
...\pci_frame_crit.v
...\pci_frame_en_crit.v
...\pci_wbr_fifo_control(1).v
...\pci_wbr_fifo_control.v
...\pci_wbs_wbb3_2_wbb2(1).v
...\pci_wbs_wbb3_2_wbb2.v
...\pci_wbw_fifo_control(1).v
...\pci_wbw_fifo_control.v
...\pci_wbw_wbr_fifos(1).v
...\pci_wbw_wbr_fifos.v
...\pci_wb_tpram.v
...\timescale(1).v
...\timescale.v