文件名称:clk_div
介绍说明－－下载内容均来自于网络，请自行研究使用
用Verilog HDL实现对时钟的四分频和16分频，并在Quartus上仿真-Clock divided by four and divided by 16, and in the Quartus simulation using Verilog HDL
(系统自动生成,下载前可以参看下载内容)
下载文件列表
div_clk\db\div_clk.asm.qmsg
.......\..\div_clk.cbx.xml
.......\..\div_clk.cmp.bpm
.......\..\div_clk.cmp.cdb
.......\..\div_clk.cmp.ecobp
.......\..\div_clk.cmp.hdb
.......\..\div_clk.cmp.kpt
.......\..\div_clk.cmp.logdb
.......\..\div_clk.cmp.rdb
.......\..\div_clk.cmp.tdb
.......\..\div_clk.cmp0.ddb
.......\..\div_clk.cmp_merge.kpt
.......\..\div_clk.db_info
.......\..\div_clk.eco.cdb
.......\..\div_clk.eds_overflow
.......\..\div_clk.fit.qmsg
.......\..\div_clk.hier_info
.......\..\div_clk.hif
.......\..\div_clk.lpc.html
.......\..\div_clk.lpc.rdb
.......\..\div_clk.lpc.txt
.......\..\div_clk.map.bpm
.......\..\div_clk.map.cdb
.......\..\div_clk.map.ecobp
.......\..\div_clk.map.hdb
.......\..\div_clk.map.kpt
.......\..\div_clk.map.logdb
.......\..\div_clk.map.qmsg
.......\..\div_clk.map_bb.cdb
.......\..\div_clk.map_bb.hdb
.......\..\div_clk.map_bb.logdb
.......\..\div_clk.pre_map.cdb
.......\..\div_clk.pre_map.hdb
.......\..\div_clk.rtlv.hdb
.......\..\div_clk.rtlv_sg.cdb
.......\..\div_clk.rtlv_sg_swap.cdb
.......\..\div_clk.sgdiff.cdb
.......\..\div_clk.sgdiff.hdb
.......\..\div_clk.sim.cvwf
.......\..\div_clk.sim.hdb
.......\..\div_clk.sim.qmsg
.......\..\div_clk.sim.rdb
.......\..\div_clk.sld_design_entry.sci
.......\..\div_clk.sld_design_entry_dsc.sci
.......\..\div_clk.syn_hier_info
.......\..\div_clk.tan.qmsg
.......\..\div_clk.tis_db_list.ddb
.......\..\div_clk.tmw_info
.......\..\div_clk_global_asgn_op.abo
.......\..\prev_cmp_div_clk.asm.qmsg
.......\..\prev_cmp_div_clk.fit.qmsg
.......\..\prev_cmp_div_clk.map.qmsg
.......\..\prev_cmp_div_clk.qmsg
.......\..\prev_cmp_div_clk.sim.qmsg
.......\..\prev_cmp_div_clk.tan.qmsg
.......\..\wed.wsf
.......\div_clk.asm.rpt
.......\div_clk.done
.......\div_clk.fit.rpt
.......\div_clk.fit.smsg
.......\div_clk.fit.summary
.......\div_clk.flow.rpt
.......\div_clk.map.rpt
.......\div_clk.map.summary
.......\div_clk.pin
.......\div_clk.pof
.......\div_clk.qpf
.......\div_clk.qsf
.......\div_clk.qws
.......\div_clk.sim.rpt
.......\div_clk.sof
.......\div_clk.tan.rpt
.......\div_clk.tan.summary
.......\div_clk.v
.......\div_clk.v.bak
.......\div_clk.vwf
.......\incremental_db\compiled_partitions\div_clk.root_partition.cmp.atm
.......\..............\...................\div_clk.root_partition.cmp.dfp
.......\..............\...................\div_clk.root_partition.cmp.hdbx
.......\..............\...................\div_clk.root_partition.cmp.kpt
.......\..............\...................\div_clk.root_partition.cmp.logdb
.......\..............\...................\div_clk.root_partition.cmp.rcf
.......\..............\...................\div_clk.root_partition.map.atm
.......\..............\...................\div_clk.root_partition.map.dpi
.......\..............\...................\div_clk.root_partition.map.hdbx
.......\..............\...................\div_clk.root_partition.map.kpt
.......\..............\README
.......\..............\compiled_partitions
.......\db
.......\incremental_db
div_clk