文件名称:vhdl-tutorial
- 所属分类：
- 文件格式
- 资源属性：
- [PDF]
- 上传时间：
- 2013-02-13
- 文件大小：
- 306kb
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- 0次
- 提 供 者：
- bikram******
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The purpose of this tutorial is to describe the modeling language VHDL. VHDL includes
facilities for describing logical structure and function of digital systems at a
number of levels of abstraction, from system level down to the gate level. It is intended,
among other things, as a modeling language for specification and simulation. We
can also use it for hardware synthesis if we restrict ourselves to a subset that can be
automatically translated into hardware.
facilities for describing logical structure and function of digital systems at a
number of levels of abstraction, from system level down to the gate level. It is intended,
among other things, as a modeling language for specification and simulation. We
can also use it for hardware synthesis if we restrict ourselves to a subset that can be
automatically translated into hardware.
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vhdl-tutorial.pdf