文件名称:vhdl-tutorial
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VHDL Tutorial, it describes the modeling language VHDL. VHDL includes
facilities for describing logical structure and function of digital systems at a
number of levels of abstraction, from system level down to the gate level. It is intended,
among other things, as a modeling language for specification and simulation. We
can also use it for hardware synthesis if we restrict ourselves to a subset that can be
automatically translated into hardware.
facilities for describing logical structure and function of digital systems at a
number of levels of abstraction, from system level down to the gate level. It is intended,
among other things, as a modeling language for specification and simulation. We
can also use it for hardware synthesis if we restrict ourselves to a subset that can be
automatically translated into hardware.
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下载文件列表
vhdl-tutorial.pdf