文件名称:Verilog
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Zr-tech开发板uart例程基于quartus的工程源代码-Zr-tech development board uart routines based quartus project source code
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下载文件列表
Verilog\db\prev_cmp_uart.asm.qmsg
.......\..\prev_cmp_uart.fit.qmsg
.......\..\prev_cmp_uart.map.qmsg
.......\..\prev_cmp_uart.qmsg
.......\..\prev_cmp_uart.tan.qmsg
.......\..\uart.asm.qmsg
.......\..\uart.asm_labs.ddb
.......\..\uart.cbx.xml
.......\..\uart.cmp.bpm
.......\..\uart.cmp.cdb
.......\..\uart.cmp.ecobp
.......\..\uart.cmp.hdb
.......\..\uart.cmp.kpt
.......\..\uart.cmp.logdb
.......\..\uart.cmp.rdb
.......\..\uart.cmp.tdb
.......\..\uart.cmp0.ddb
.......\..\uart.cmp2.ddb
.......\..\uart.cmp_merge.kpt
.......\..\uart.db_info
.......\..\uart.eco.cdb
.......\..\uart.fit.qmsg
.......\..\uart.hier_info
.......\..\uart.hif
.......\..\uart.lpc.html
.......\..\uart.lpc.rdb
.......\..\uart.lpc.txt
.......\..\uart.map.bpm
.......\..\uart.map.cdb
.......\..\uart.map.ecobp
.......\..\uart.map.hdb
.......\..\uart.map.kpt
.......\..\uart.map.logdb
.......\..\uart.map.qmsg
.......\..\uart.map_bb.cdb
.......\..\uart.map_bb.hdb
.......\..\uart.map_bb.logdb
.......\..\uart.pre_map.cdb
.......\..\uart.pre_map.hdb
.......\..\uart.rtlv.hdb
.......\..\uart.rtlv_sg.cdb
.......\..\uart.rtlv_sg_swap.cdb
.......\..\uart.sgdiff.cdb
.......\..\uart.sgdiff.hdb
.......\..\uart.sld_design_entry.sci
.......\..\uart.sld_design_entry_dsc.sci
.......\..\uart.syn_hier_info
.......\..\uart.tan.qmsg
.......\..\uart.tis_db_list.ddb
.......\..\uart.tmw_info
.......\..\uart_global_asgn_op.abo
.......\incremental_db\compiled_partitions\uart.root_partition.cmp.atm
.......\..............\...................\uart.root_partition.cmp.dfp
.......\..............\...................\uart.root_partition.cmp.hdbx
.......\..............\...................\uart.root_partition.cmp.kpt
.......\..............\...................\uart.root_partition.cmp.logdb
.......\..............\...................\uart.root_partition.cmp.rcf
.......\..............\...................\uart.root_partition.map.atm
.......\..............\...................\uart.root_partition.map.dpi
.......\..............\...................\uart.root_partition.map.hdbx
.......\..............\...................\uart.root_partition.map.kpt
.......\..............\README
.......\pin\CORE2-5SD-PERI1-SLOT1-PERI2-SLOT2.tcl
.......\...\CORE2-5U-PERI1-SLOT1-PERI2-SLOT2.tcl
.......\...\COREC-240U-PERI1-SLOT1-PERI2-SLOT2.tcl
.......\uart.asm.rpt
.......\uart.cdf
.......\uart.done
.......\uart.dpf
.......\uart.fit.rpt
.......\uart.fit.smsg
.......\uart.fit.summary
.......\uart.flow.rpt
.......\uart.map.rpt
.......\uart.map.summary
.......\uart.pin
.......\uart.pof
.......\uart.qpf
.......\uart.qsf
.......\uart.qws
.......\uart.sof
.......\uart.tan.rpt
.......\uart.tan.summary
.......\uart.v
.......\uart_assignment_defaults.qdf
.......\incremental_db\compiled_partitions
.......\db
.......\incremental_db
.......\pin
Verilog