文件名称:Verilog
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RAM ,IFFO实现字节的存储器设计，经过验证-RAM, IFFO bytes of memory design, proven
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下载文件列表
Verilog
.......\BitBLT.tcl
.......\BitBlt_top.v
.......\Color_LUT.mif
.......\PLL_cycloneii.v
.......\ROM_COLOR_LUT.v
.......\anywhere_avalon_bitblt
.......\......................\cb_generator.pl
.......\......................\class.ptf
.......\......................\hdl
.......\......................\...\anywhere_avalon_bitblt.v
.......\......................\...\bitblt_16to32.v
.......\......................\...\bitblt_avalon_burstread.v
.......\......................\...\bitblt_avalon_burstwrite.v
.......\......................\...\bitblt_avalon_slave.v
.......\......................\...\bitblt_dataproc.v
.......\......................\...\bitblt_dataproc_dest.v
.......\......................\...\bitblt_dataproc_src.v
.......\......................\...\bitblt_dataproc_src_dest.v
.......\......................\...\bitblt_dest_32to16.v
.......\......................\...\bitblt_mainstate.v
.......\......................\...\bitblt_rd_dest_master.v
.......\......................\...\bitblt_rd_src_master.v
.......\......................\...\bitblt_src_change_color_format.v
.......\......................\...\bitblt_src_fifo1_to_fifo2_32to16.v
.......\......................\...\bitblt_src_fifo1_to_fifo2_color_expan.v
.......\......................\...\bitblt_src_fifo1_to_fifo2_color_lut.v
.......\......................\...\bitblt_wr_dest_master.v
.......\......................\...\lpm_fifo_16_256.v
.......\......................\...\lpm_fifo_32_128.v
.......\......................\...\lpm_fifo_32_128_showhead.v
.......\......................\...\lpm_mult11.v
.......\......................\inc
.......\......................\...\anywhere_avalon_bitblt_regs.h
.......\anywhere_lcd_controller
.......\.......................\cb_generator.pl
.......\.......................\class.ptf
.......\.......................\hdl
.......\.......................\...\Alpha_Pipe.v
.......\.......................\...\Asyn_FIFO.v
.......\.......................\...\BG_FIFO.v
.......\.......................\...\BG_Layer.v
.......\.......................\...\FG1_FIFO.v
.......\.......................\...\FG1_Layer.v
.......\.......................\...\FG2_FIFO.v
.......\.......................\...\FG2_Layer.v
.......\.......................\...\FIFO_32to16.v
.......\.......................\...\FIFO_32to8.v
.......\.......................\...\ROM_COLOR_LUT.v
.......\.......................\...\Register_slave.v
.......\.......................\...\Timing_Engine.v
.......\.......................\...\anywhere_LCD_controller.v
.......\.......................\...\data_fetcher.v
.......\.......................\...\data_mixer.v
.......\.......................\...\lpm_mul.v
.......\.......................\...\master.v
.......\.......................\...\scanner.v
.......\.......................\inc
.......\.......................\...\anywhere_avalon_lcd_regs.h