文件名称:clock
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vhdl语言实现的时钟功能的quartus工程。在FPGA上运行可以得到时钟效果，并有调节功能。-vhdl language to achieve clock quartus project. Can get the clock running on the FPGA results, and regulatory function.
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下载文件列表
4-5good kid\chuzhi.bmp
...........\.lock\clock.asm.rpt
...........\.....\clock.done
...........\.....\clock.fit.eqn
...........\.....\clock.fit.rpt
...........\.....\clock.fit.summary
...........\.....\clock.flow.rpt
...........\.....\clock.map.eqn
...........\.....\clock.map.rpt
...........\.....\clock.map.summary
...........\.....\clock.pin
...........\.....\clock.pof
...........\.....\clock.qpf
...........\.....\clock.qsf
...........\.....\clock.qws
...........\.....\clock.sof
...........\.....\clock.tan.rpt
...........\.....\clock.tan.summary
...........\.....\clock.vhd
...........\.....\cmp_state.ini
...........\.....\db\add_sub_ke8.tdf
...........\.....\..\add_sub_le8.tdf
...........\.....\..\add_sub_ma8.tdf
...........\.....\..\add_sub_me8.tdf
...........\.....\..\add_sub_ne8.tdf
...........\.....\..\add_sub_oe8.tdf
...........\.....\..\alt_u_div_bld.tdf
...........\.....\..\alt_u_div_dld.tdf
...........\.....\..\clock.asm.qmsg
...........\.....\..\clock.cbx.xml
...........\.....\..\clock.cmp.cdb
...........\.....\..\clock.cmp.hdb
...........\.....\..\clock.cmp.rdb
...........\.....\..\clock.cmp.tdb
...........\.....\..\clock.cmp0.ddb
...........\.....\..\clock.db_info
...........\.....\..\clock.eco.cdb
...........\.....\..\clock.fit.qmsg
...........\.....\..\clock.hier_info
...........\.....\..\clock.hif
...........\.....\..\clock.map.cdb
...........\.....\..\clock.map.hdb
...........\.....\..\clock.map.qmsg
...........\.....\..\clock.pre_map.cdb
...........\.....\..\clock.pre_map.hdb
...........\.....\..\clock.psp
...........\.....\..\clock.rtlv.hdb
...........\.....\..\clock.rtlv_sg.cdb
...........\.....\..\clock.rtlv_sg_swap.cdb
...........\.....\..\clock.sgdiff.cdb
...........\.....\..\clock.sgdiff.hdb
...........\.....\..\clock.signalprobe.cdb
...........\.....\..\clock.sld_design_entry.sci
...........\.....\..\clock.sld_design_entry_dsc.sci
...........\.....\..\clock.syn_hier_info
...........\.....\..\clock.tan.qmsg
...........\.....\..\clock_cmp.qrpt
...........\.....\..\lpm_divide_hlf.tdf
...........\.....\..\lpm_divide_ilf.tdf
...........\.....\..\lpm_divide_kdf.tdf
...........\.....\..\lpm_divide_ldf.tdf
...........\.....\..\sign_div_unsign_jhg.tdf
...........\.....\..\sign_div_unsign_khg.tdf
...........\clock.bsf
...........\clock.vhd
...........\cmp_state.ini
...........\db\add_sub_ke8.tdf
...........\..\add_sub_le8.tdf
...........\..\add_sub_ma8.tdf
...........\..\add_sub_me8.tdf
...........\..\add_sub_ne8.tdf
...........\..\add_sub_oe8.tdf
...........\..\alt_u_div_bld.tdf
...........\..\alt_u_div_dld.tdf
...........\..\Design0.asm.qmsg
...........\..\Design0.cbx.xml
...........\..\Design0.cmp.cdb
...........\..\Design0.cmp.hdb
...........\..\Design0.cmp.rdb
...........\..\Design0.cmp.tdb
...........\..\Design0.cmp0.ddb
...........\..\Design0.db_info
...........\..\Design0.eco.cdb
...........\..\Design0.fit.qmsg
...........\..\Design0.hier_info
...........\..\Design0.hif
...........\..\Design0.map.cdb
...........\..\Design0.map.hdb
...........\..\Design0.map.qmsg
...........\..\Design0.pre_map.cdb
...........\..\Design0.pre_map.hdb
...........\..\Design0.psp
...........\..\Design0.rtlv.hdb
...........\..\Design0.rtlv_sg.cdb
...........\..\Design0.rtlv_sg_swap.cdb
...........\..\Design0.sgdiff.cdb
...........\..\Design0.sgdiff.hdb
...........\..\Design0.signalprobe.cdb
...........\..\Design0.sld_design_entry.sci
...........\..\Design0.sld_design_entry_dsc.sci
...........\.lock\clock.asm.rpt
...........\.....\clock.done
...........\.....\clock.fit.eqn
...........\.....\clock.fit.rpt
...........\.....\clock.fit.summary
...........\.....\clock.flow.rpt
...........\.....\clock.map.eqn
...........\.....\clock.map.rpt
...........\.....\clock.map.summary
...........\.....\clock.pin
...........\.....\clock.pof
...........\.....\clock.qpf
...........\.....\clock.qsf
...........\.....\clock.qws
...........\.....\clock.sof
...........\.....\clock.tan.rpt
...........\.....\clock.tan.summary
...........\.....\clock.vhd
...........\.....\cmp_state.ini
...........\.....\db\add_sub_ke8.tdf
...........\.....\..\add_sub_le8.tdf
...........\.....\..\add_sub_ma8.tdf
...........\.....\..\add_sub_me8.tdf
...........\.....\..\add_sub_ne8.tdf
...........\.....\..\add_sub_oe8.tdf
...........\.....\..\alt_u_div_bld.tdf
...........\.....\..\alt_u_div_dld.tdf
...........\.....\..\clock.asm.qmsg
...........\.....\..\clock.cbx.xml
...........\.....\..\clock.cmp.cdb
...........\.....\..\clock.cmp.hdb
...........\.....\..\clock.cmp.rdb
...........\.....\..\clock.cmp.tdb
...........\.....\..\clock.cmp0.ddb
...........\.....\..\clock.db_info
...........\.....\..\clock.eco.cdb
...........\.....\..\clock.fit.qmsg
...........\.....\..\clock.hier_info
...........\.....\..\clock.hif
...........\.....\..\clock.map.cdb
...........\.....\..\clock.map.hdb
...........\.....\..\clock.map.qmsg
...........\.....\..\clock.pre_map.cdb
...........\.....\..\clock.pre_map.hdb
...........\.....\..\clock.psp
...........\.....\..\clock.rtlv.hdb
...........\.....\..\clock.rtlv_sg.cdb
...........\.....\..\clock.rtlv_sg_swap.cdb
...........\.....\..\clock.sgdiff.cdb
...........\.....\..\clock.sgdiff.hdb
...........\.....\..\clock.signalprobe.cdb
...........\.....\..\clock.sld_design_entry.sci
...........\.....\..\clock.sld_design_entry_dsc.sci
...........\.....\..\clock.syn_hier_info
...........\.....\..\clock.tan.qmsg
...........\.....\..\clock_cmp.qrpt
...........\.....\..\lpm_divide_hlf.tdf
...........\.....\..\lpm_divide_ilf.tdf
...........\.....\..\lpm_divide_kdf.tdf
...........\.....\..\lpm_divide_ldf.tdf
...........\.....\..\sign_div_unsign_jhg.tdf
...........\.....\..\sign_div_unsign_khg.tdf
...........\clock.bsf
...........\clock.vhd
...........\cmp_state.ini
...........\db\add_sub_ke8.tdf
...........\..\add_sub_le8.tdf
...........\..\add_sub_ma8.tdf
...........\..\add_sub_me8.tdf
...........\..\add_sub_ne8.tdf
...........\..\add_sub_oe8.tdf
...........\..\alt_u_div_bld.tdf
...........\..\alt_u_div_dld.tdf
...........\..\Design0.asm.qmsg
...........\..\Design0.cbx.xml
...........\..\Design0.cmp.cdb
...........\..\Design0.cmp.hdb
...........\..\Design0.cmp.rdb
...........\..\Design0.cmp.tdb
...........\..\Design0.cmp0.ddb
...........\..\Design0.db_info
...........\..\Design0.eco.cdb
...........\..\Design0.fit.qmsg
...........\..\Design0.hier_info
...........\..\Design0.hif
...........\..\Design0.map.cdb
...........\..\Design0.map.hdb
...........\..\Design0.map.qmsg
...........\..\Design0.pre_map.cdb
...........\..\Design0.pre_map.hdb
...........\..\Design0.psp
...........\..\Design0.rtlv.hdb
...........\..\Design0.rtlv_sg.cdb
...........\..\Design0.rtlv_sg_swap.cdb
...........\..\Design0.sgdiff.cdb
...........\..\Design0.sgdiff.hdb
...........\..\Design0.signalprobe.cdb
...........\..\Design0.sld_design_entry.sci
...........\..\Design0.sld_design_entry_dsc.sci