文件名称:usb1.1
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 62kb
- 下载次数：
- 0次
- 提 供 者：
- huipe*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
下载
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失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
USB 1.1的verilog代码，已通过fpga 程序源代码内容-Verilog code for USB 1.1, has passed through the contents of the source code fpga
(系统自动生成,下载前可以参看下载内容)
下载文件列表
usb1.1\usb1.1\usb1_1_deviceip\testbench\tests.v
......\......\...............\.........\tests_lib.v
......\......\...............\.........\test_bench_top.v
......\......\...............\.........\timescale.v
......\......\...............\sim\sim1.txt
......\......\...............\...\sim2.txt
......\......\...............\...\sim3.txt
......\......\...............\RTL_code\timescale.v
......\......\...............\........\usb1_core.v
......\......\...............\........\usb1_crc16.v
......\......\...............\........\usb1_crc5.v
......\......\...............\........\usb1_ctrl.v
......\......\...............\........\usb1_defines.v
......\......\...............\........\usb1_fifo2.v
......\......\...............\........\usb1_idma.v
......\......\...............\........\usb1_pa.v
......\......\...............\........\usb1_pd.v
......\......\...............\........\usb1_pe.v
......\......\...............\........\usb1_pl.v
......\......\...............\........\usb1_rom1.v
......\......\...............\........\usb1_utmi_if.v
......\......\...............\doc\read_me_1.1.txt
......\......\...............\...\read_me_1.2.txt
......\......\...............\...\sucess_story.txt
......\......\USB1_1 PHY\timescale.v
......\......\..........\USB 1.1 PHY.txt
......\......\..........\usb_phy.v
......\......\..........\usb_rx_phy.v
......\......\..........\usb_tx_phy.v
......\......\usb1_1_deviceip\testbench
......\......\...............\sim
......\......\...............\RTL_code
......\......\...............\doc
......\......\usb1_1_deviceip
......\......\USB1_1 PHY
......\usb1.1
usb1.1
......\......\...............\.........\tests_lib.v
......\......\...............\.........\test_bench_top.v
......\......\...............\.........\timescale.v
......\......\...............\sim\sim1.txt
......\......\...............\...\sim2.txt
......\......\...............\...\sim3.txt
......\......\...............\RTL_code\timescale.v
......\......\...............\........\usb1_core.v
......\......\...............\........\usb1_crc16.v
......\......\...............\........\usb1_crc5.v
......\......\...............\........\usb1_ctrl.v
......\......\...............\........\usb1_defines.v
......\......\...............\........\usb1_fifo2.v
......\......\...............\........\usb1_idma.v
......\......\...............\........\usb1_pa.v
......\......\...............\........\usb1_pd.v
......\......\...............\........\usb1_pe.v
......\......\...............\........\usb1_pl.v
......\......\...............\........\usb1_rom1.v
......\......\...............\........\usb1_utmi_if.v
......\......\...............\doc\read_me_1.1.txt
......\......\...............\...\read_me_1.2.txt
......\......\...............\...\sucess_story.txt
......\......\USB1_1 PHY\timescale.v
......\......\..........\USB 1.1 PHY.txt
......\......\..........\usb_phy.v
......\......\..........\usb_rx_phy.v
......\......\..........\usb_tx_phy.v
......\......\usb1_1_deviceip\testbench
......\......\...............\sim
......\......\...............\RTL_code
......\......\...............\doc
......\......\usb1_1_deviceip
......\......\USB1_1 PHY
......\usb1.1
usb1.1