adder\adder.v

.....\adder_testbench.do

.....\adder_testbench.v

.....\transcript

.....\vsim.wlf

.....\chart\图1-3.bmp

.....\.....\图1-4.bmp

.....\.....\图1-5.bmp

.....\.....\图1-6.bmp

.....\.....\图1-7.bmp

.....\.....\图1-8.bmp

.....\work\_info

.....\....\adder\_primary.vhd

.....\....\.....\transcript

.....\....\.....\verilog.txt.asm

.....\....\.....\_primary.dat

.....\....\.....\verilog.asm

.....\....\....._testbench\_primary.vhd

.....\....\...............\_primary.dat

.....\....\...............\verilog.asm

.....\....\_opt\work__info

.....\....\....\work_adder_fast.dt2

.....\....\....\work_adder_testbench_fast.asm

.....\....\....\work_adder_testbench_fast.dt2

.....\....\....\_deps

.....\adder_testbench.v.bak

.....\adder.mpf.bak

.....\wave.do

.....\adder.mpf

.....\adder.cr.mti

.....\work\adder

.....\....\adder_testbench

.....\....\_temp

.....\....\_opt

.....\chart

.....\work

adder