文件名称:Minirisc
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [C/C++] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 85kb
- 下载次数：
- 0次
- 提 供 者：
- nic***
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
微型RISC处理器ip核，可以直接使用，包含详细的结构和端口介绍-Ip mini RISC processor core, can be used directly, contains a detailed descr iption of the structure and the port
(系统自动生成,下载前可以参看下载内容)
下载文件列表
minirisc\minirisc\CVS\Entries
........\........\...\Repository
........\........\...\Root
........\........\CVS
........\........\README.txt
........\........\scode\CVS\Entries
........\........\.....\...\Repository
........\........\.....\...\Root
........\........\.....\CVS
........\........\.....\hex2v.c
........\........\.....\rf1.asm
........\........\.....\rf1.rom
........\........\.....\rf2.asm
........\........\.....\rf2.rom
........\........\.....\rf3.asm
........\........\.....\rf3.rom
........\........\.....\sanity1.asm
........\........\.....\sanity1.rom
........\........\.....\sanity2.asm
........\........\.....\sanity2.rom
........\........\.....\tmr_wdt.asm
........\........\.....\tmr_wdt.rom
........\........\scode
........\........\.im\CVS\Entries
........\........\...\...\Repository
........\........\...\...\Root
........\........\...\CVS
........\........\...\run
........\........\sim
........\........\verilog\core\alu.v
........\........\.......\....\CVS\Entries
........\........\.......\....\...\Repository
........\........\.......\....\...\Root
........\........\.......\....\CVS
........\........\.......\....\presclr_wdt.v
........\........\.......\....\primitives.v
........\........\.......\....\primitives_xilinx.v
........\........\.......\....\register_file.v
........\........\.......\....\risc_core.v
........\........\.......\....\risc_core_top.v
........\........\.......\core
........\........\.......\CVS\Entries
........\........\.......\...\Repository
........\........\.......\...\Root
........\........\.......\CVS
........\........\.......\testbench\CVS\Entries
........\........\.......\.........\...\Repository
........\........\.......\.........\...\Root
........\........\.......\.........\CVS
........\........\.......\.........\prog_mem.v
........\........\.......\.........\test.v
........\........\.......\testbench
........\........\verilog
........\........\xilinx_primitives.zip
........\minirisc
minirisc
........\........\...\Repository
........\........\...\Root
........\........\CVS
........\........\README.txt
........\........\scode\CVS\Entries
........\........\.....\...\Repository
........\........\.....\...\Root
........\........\.....\CVS
........\........\.....\hex2v.c
........\........\.....\rf1.asm
........\........\.....\rf1.rom
........\........\.....\rf2.asm
........\........\.....\rf2.rom
........\........\.....\rf3.asm
........\........\.....\rf3.rom
........\........\.....\sanity1.asm
........\........\.....\sanity1.rom
........\........\.....\sanity2.asm
........\........\.....\sanity2.rom
........\........\.....\tmr_wdt.asm
........\........\.....\tmr_wdt.rom
........\........\scode
........\........\.im\CVS\Entries
........\........\...\...\Repository
........\........\...\...\Root
........\........\...\CVS
........\........\...\run
........\........\sim
........\........\verilog\core\alu.v
........\........\.......\....\CVS\Entries
........\........\.......\....\...\Repository
........\........\.......\....\...\Root
........\........\.......\....\CVS
........\........\.......\....\presclr_wdt.v
........\........\.......\....\primitives.v
........\........\.......\....\primitives_xilinx.v
........\........\.......\....\register_file.v
........\........\.......\....\risc_core.v
........\........\.......\....\risc_core_top.v
........\........\.......\core
........\........\.......\CVS\Entries
........\........\.......\...\Repository
........\........\.......\...\Root
........\........\.......\CVS
........\........\.......\testbench\CVS\Entries
........\........\.......\.........\...\Repository
........\........\.......\.........\...\Root
........\........\.......\.........\CVS
........\........\.......\.........\prog_mem.v
........\........\.......\.........\test.v
........\........\.......\testbench
........\........\verilog
........\........\xilinx_primitives.zip
........\minirisc
minirisc