文件名称:minirisc
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [C/C++] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 84kb
- 下载次数：
- 0次
- 提 供 者：
- J***
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
minirisc Mini-RISC CPU-Microcontroller that is compatible with the PIC 16C57 from Microchip
Mini-RISC CPU-Microcontroller ＩＰ核
-minirisc Mini-bit RISC CPU-Microcontroller that is compatible with the PIC 16C57 from Micro chip Mini-bit RISC CPU-Microcontroller IP Core
Mini-RISC CPU-Microcontroller ＩＰ核
-minirisc Mini-bit RISC CPU-Microcontroller that is compatible with the PIC 16C57 from Micro chip Mini-bit RISC CPU-Microcontroller IP Core
相关搜索： risc
(系统自动生成,下载前可以参看下载内容)
下载文件列表
minirisc
........\CVS
........\...\Entries
........\...\Repository
........\...\Root
........\README.txt
........\scode
........\.....\CVS
........\.....\...\Entries
........\.....\...\Repository
........\.....\...\Root
........\.....\hex2v.c
........\.....\rf1.asm
........\.....\rf1.rom
........\.....\rf2.asm
........\.....\rf2.rom
........\.....\rf3.asm
........\.....\rf3.rom
........\.....\sanity1.asm
........\.....\sanity1.rom
........\.....\sanity2.asm
........\.....\sanity2.rom
........\.....\tmr_wdt.asm
........\.....\tmr_wdt.rom
........\sim
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\...\run
........\verilog
........\.......\core
........\.......\....\alu.v
........\.......\....\CVS
........\.......\....\...\Entries
........\.......\....\...\Repository
........\.......\....\...\Root
........\.......\....\presclr_wdt.v
........\.......\....\primitives.v
........\.......\....\primitives_xilinx.v
........\.......\....\register_file.v
........\.......\....\risc_core.v
........\.......\....\risc_core_top.v
........\.......\CVS
........\.......\...\Entries
........\.......\...\Repository
........\.......\...\Root
........\.......\testbench
........\.......\.........\CVS
........\.......\.........\...\Entries
........\.......\.........\...\Repository
........\.......\.........\...\Root
........\.......\.........\prog_mem.v
........\.......\.........\test.v
........\xilinx_primitives.zip
........\CVS
........\...\Entries
........\...\Repository
........\...\Root
........\README.txt
........\scode
........\.....\CVS
........\.....\...\Entries
........\.....\...\Repository
........\.....\...\Root
........\.....\hex2v.c
........\.....\rf1.asm
........\.....\rf1.rom
........\.....\rf2.asm
........\.....\rf2.rom
........\.....\rf3.asm
........\.....\rf3.rom
........\.....\sanity1.asm
........\.....\sanity1.rom
........\.....\sanity2.asm
........\.....\sanity2.rom
........\.....\tmr_wdt.asm
........\.....\tmr_wdt.rom
........\sim
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\...\run
........\verilog
........\.......\core
........\.......\....\alu.v
........\.......\....\CVS
........\.......\....\...\Entries
........\.......\....\...\Repository
........\.......\....\...\Root
........\.......\....\presclr_wdt.v
........\.......\....\primitives.v
........\.......\....\primitives_xilinx.v
........\.......\....\register_file.v
........\.......\....\risc_core.v
........\.......\....\risc_core_top.v
........\.......\CVS
........\.......\...\Entries
........\.......\...\Repository
........\.......\...\Root
........\.......\testbench
........\.......\.........\CVS
........\.......\.........\...\Entries
........\.......\.........\...\Repository
........\.......\.........\...\Root
........\.......\.........\prog_mem.v
........\.......\.........\test.v
........\xilinx_primitives.zip