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[VHDL编程] 5.44业务配置
说明:是一种常用的router acl配置,就是一种常用的router acl配置(It's a common router ACL configuration, a common router ACL configuration)<jiang564564> 在 2024-12-27 上传 | 大小:1kb | 下载:0
[VHDL编程] BluetoothApis
说明:dsaf,sdv,fsdj,hva,dj lbw,jbwdhv,bjOFVUOVWHCJVB,ohjvcadshjvah,xvhasvah,vcsdhck(dsv,dsjhdfasd,daokhvapHFUWP,FDKAJNDBVHIIHCNDSJ,sandiwv)<ewqwew> 在 2024-12-27 上传 | 大小:83kb | 下载:0
[VHDL编程] an495_design_example
说明:ALTERA ers that having account in so they can help you to get your files. But to prevent overloading and abusing; We have some.ers that having account in so they can help you to get your files. But to prevent overloading<yellowhataq> 在 2024-12-27 上传 | 大小:417kb | 下载:0
[VHDL编程] an496_design_example
说明:MAX II that having account in so they can help you to get your files. But to prevent overloading and abusing; We have some. ers that having account in so they can help you to get your files. But to prevent overloading a<yellowhataq> 在 2024-12-27 上传 | 大小:229kb | 下载:0
[VHDL编程] Greedy_snake
说明:贪吃蛇,用SPARTAN6系列FPGA实现的贪吃蛇例程,用ISE14.7打开即可,Verilog语言(greedy_snake.rar The realization of the snake in the Verilog language Using ISE14.7)<余杭美吧> 在 2024-12-27 上传 | 大小:6.99mb | 下载:0
[VHDL编程] 51CTO下载-VerilogHDL程序设计实例详解12
说明:VerilogHDL 程序设计实例详解(VerilogHDL program design example detailed solution)<pacl> 在 2024-12-27 上传 | 大小:1.73mb | 下载:0
[VHDL编程] 2mw PMSG Complete data
说明:ndbnfbwfnbbfwhdbfhhwdbhfhbhdhsfbubhb<maharshi> 在 2024-12-27 上传 | 大小:1.01mb | 下载:0
[VHDL编程] UART
说明:本人用verilog编写的UART协议,经测试可用。(I am prepared to use verilog UART protocol, the test is available.)<chenpeiweiweiwei> 在 2024-12-27 上传 | 大小:505kb | 下载:0
[VHDL编程] S02_CH02_MIO
说明:xilinx zynq的mio口测试工程,内容很详细(zynq mio test,about zynq mio pin test,very useful)<美机灵> 在 2024-12-27 上传 | 大小:19mb | 下载:0