资源列表
[VHDL编程] ADC_INTERFACE
说明:it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and<yasir ateeq> 在 2024-11-18 上传 | 大小:6kb | 下载:0
[VHDL编程] FIFO
说明:it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which da<yasir ateeq> 在 2024-11-18 上传 | 大小:31kb | 下载:0
[VHDL编程] traffic_controller
说明:it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.-it is a verilog code writt<yasir ateeq> 在 2024-11-18 上传 | 大小:34kb | 下载:0
[VHDL编程] UART_for_FPGArar
说明:it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state mac<yasir ateeq> 在 2024-11-18 上传 | 大小:5kb | 下载:0
[VHDL编程] ise_book
说明:实现交通灯,两条马路,仿真成功,还有实验说明书-traffic lights<hongbingying> 在 2024-11-18 上传 | 大小:106kb | 下载:0
[VHDL编程] vga_display
说明:VGA controller源码及显示汉字和ascii字符的c代码实例,已在DE2-70上实现-vga_controller source code and c code which can display chinese charactors and ASCII code on the VGA<> 在 2024-11-18 上传 | 大小:297kb | 下载:0