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[VHDL编程] DDS_FINAL
说明:My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave a<Raju Kumar> 在 2025-01-24 上传 | 大小:427kb | 下载:0
[VHDL编程] spasion_flash_verilog_model
说明:verilog模型,用于仿真flash,可以快速地看懂-verilog model for flash controller specified for spasion flash, please download it look at it<jiangwen> 在 2025-01-24 上传 | 大小:221kb | 下载:0