资源列表
[VHDL编程] FPGA-HDLC-design
说明:基于FPGA的HDLC协议控制器的设计。FPGA-based HDLC protocol controller design. Pdf-FPGA-based HDLC protocol controller design. Pdf<iriu> 在 2025-02-19 上传 | 大小:1.52mb | 下载:0
[VHDL编程] fast_antilog_latest.tar
说明:Anti-Logarithm (square-root), base-2, single-cycle<aliakbar> 在 2025-02-19 上传 | 大小:1kb | 下载:0
[VHDL编程] cf_fp_mul_latest.tar
说明:CF Floating Point Multiplier<aliakbar> 在 2025-02-19 上传 | 大小:573kb | 下载:0
[VHDL编程] AsicVhdlBasicLab_Vhdl
说明:Asic Vhdl Basic Ans Lab_Vhdl Examples_microprocessor (VHDL)desingn<aliakbar> 在 2025-02-19 上传 | 大小:4.22mb | 下载:0
[VHDL编程] vhdl-pipeline-mips_latest.tar
说明:pipeline mips in vhdl<aliakbar> 在 2025-02-19 上传 | 大小:1.08mb | 下载:0
[VHDL编程] rfid_latest.tar
说明:rfid tag and reader with VHDL for FPGA<aliakbar> 在 2025-02-19 上传 | 大小:1.5mb | 下载:0
[VHDL编程] Constraint-Based-Verification
说明:系統化驗証方法及實例探討Assertion, Constraint synthesis-Electronic Design complexity getting higher, the verification work needs to be fully understood<samuel chuang> 在 2025-02-19 上传 | 大小:1.57mb | 下载:1
[VHDL编程] cf_fft_latest.tar
说明:The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks are isolated from each other using memory interleavers. This FFT can perform calculations on continuous streaming data<amin> 在 2025-02-19 上传 | 大小:2.98mb | 下载:0
[VHDL编程] system05_latest.tar
说明:6805 compatible CPU Core 6805 compatible core - 4 x 8 bit Parallel I/O ports - Dual 8 bit Timer - MiniUART compatible with 6850 ACIA. - Runs with an E clock of 12.5MHz and system clock of 25MHz<amin> 在 2025-02-19 上传 | 大小:29kb | 下载:0
[VHDL编程] fpu100_latest.tar
说明:This a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Stan<amin> 在 2025-02-19 上传 | 大小:1.88mb | 下载:0