资源列表
[VHDL编程] A_VHDL_Timer
说明：8254计数器fpga实现vhdl语言英文说明文档-8254 counter vhdl fpga implementation language English documentation<日三省吾身> 在 2025-03-01 上传 | 大小：329kb | 下载：0
[VHDL编程] vhdl_division
说明：vhdl设计，各种分频方式包括实例，非常实用-vhdl design, a variety of ways, including instances of frequency, very useful<日三省吾身> 在 2025-03-01 上传 | 大小：412kb | 下载：1
[VHDL编程] VHDL_study
说明：vhdl实用教程，经典教程，本书特意做了书签，方便初学者查询-vhdl practical course, classic tutorial, the book deliberately made bookmarks, easy for beginners query<日三省吾身> 在 2025-03-01 上传 | 大小：3.62mb | 下载：0
[VHDL编程] FPGA_interview
说明：fpga各大公司面试笔试数电部分，内容详尽-number of major companies fpga electrical part of the written interview, detailed<日三省吾身> 在 2025-03-01 上传 | 大小：24kb | 下载：0
[VHDL编程] bit_stuffer
说明：Bit stuffing is used for various purposes, such as for bringing bit streams that do not necessarily have the same or rationally related bit rates up to a common rate, or to fill buffers or fr a mes. The location of the s<swapnil> 在 2025-03-01 上传 | 大小：1kb | 下载：0
[VHDL编程] comparator
说明：comparator it comparea two input and give its output<swapnil> 在 2025-03-01 上传 | 大小：1kb | 下载：0
[VHDL编程] randon_numder_generator
说明：random number generator it generate random number continousely on clk pulse<swapnil> 在 2025-03-01 上传 | 大小：3kb | 下载：0
[VHDL编程] parity_generator
说明：parity generator Parity bits are extra signals which are added to a data word to enable error checking. There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output if the<swapnil> 在 2025-03-01 上传 | 大小：20kb | 下载：0
[VHDL编程] BCD_COUNTER
说明：Binary Counting A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cyc<swapnil> 在 2025-03-01 上传 | 大小：61kb | 下载：0
[VHDL编程] PRIORITY_ENCODER
说明：A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero<swapnil> 在 2025-03-01 上传 | 大小：107kb | 下载：0
[VHDL编程] CPLD_DEMO_OK
说明：可以给VHDL初学者看的实例，全部经过验证-VHDL beginners can see examples of all the proven<王金凤> 在 2025-03-01 上传 | 大小：1.03mb | 下载：0