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[VHDL编程] complement_adder
说明:十六位补码加法器,输入为两个16位补码,输出和为17位补码,不虚溢出标志。-Sixteen complement adder, the input to complement the two 16-bit, output, and for the 17 complement, not virtual overflow flag.<JTEven> 在 2025-03-16 上传 | 大小:206kb | 下载:0
[VHDL编程] adder_32bits
说明:32位进位选择加法器,预置逻辑0和逻辑1,各模块并行运行,只要通过进位位选择逻辑0或者逻辑1即可,提高了运行速度。-32-bit carry select adder, preset logic 0 and logic 1, the modules run in parallel, as long as through the carry bit selection logic 0 or logic 1 can improve the<JTEven> 在 2025-03-16 上传 | 大小:390kb | 下载:0
[VHDL编程] VerilogHDL_En
说明:this is a working draft containing preliminary mate- rial, some of which the reader is likely to nd obscure.-The Verilog Formal Equivalence (VFE) Project is funded by the U.K. Engineering and Physical Sciences Resea<guxiaozhong> 在 2025-03-16 上传 | 大小:300kb | 下载:0