文件名称:complement_adder
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十六位补码加法器，输入为两个16位补码，输出和为17位补码，不虚溢出标志。-Sixteen complement adder, the input to complement the two 16-bit, output, and for the 17 complement, not virtual overflow flag.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
complement_adder\complement_adder\.lso
................\................\adder_4bits.udo
................\................\adder_4bits.v
................\................\complement_adder.ise
................\................\complement_adder.ise_ISE_Backup
................\................\complement_adder.ntrc_log
................\................\complement_adder.restore
................\................\complement_adder_tb.fdo
................\................\complement_adder_tb.udo
................\................\complement_adder_tb.v
................\................\conditional_adder_4bits.cmd_log
................\................\conditional_adder_4bits.lso
................\................\conditional_adder_4bits.ngc
................\................\conditional_adder_4bits.ngr
................\................\conditional_adder_4bits.prj
................\................\conditional_adder_4bits.stx
................\................\conditional_adder_4bits.syr
................\................\conditional_adder_4bits.v
................\................\conditional_adder_4bits.xst
................\................\conditional_adder_4bits_summary.html
................\................\mux.v
................\................\transcript
................\................\vsim.wlf
................\................\work\adder_4bits\verilog.asm
................\................\....\...........\_primary.dat
................\................\....\...........\_primary.vhd
................\................\....\complement_adder\verilog.asm
................\................\....\................\_primary.dat
................\................\....\................\_primary.vhd
................\................\....\................_tb\verilog.asm
................\................\....\...................\_primary.dat
................\................\....\...................\_primary.vhd
................\................\....\..nditional_adder_4bits\verilog.asm
................\................\....\.......................\_primary.dat
................\................\....\.......................\_primary.vhd
................\................\....\full_adder\verilog.asm
................\................\....\..........\_primary.dat
................\................\....\..........\_primary.vhd
................\................\....\glbl\verilog.asm
................\................\....\....\_primary.dat
................\................\....\....\_primary.vhd
................\................\....\mux\verilog.asm
................\................\....\...\_primary.dat
................\................\....\...\_primary.vhd
................\................\....\_info
................\................\xst\dump.xst\conditional_adder_4bits.prj\ntrc.scr
................\................\...\work\hdllib.ref
................\................\...\....\vlg10\conditional__adder__4bits.bin
................\................\...\....\...65\adder__4bits.bin
................\................\...\....\....6\mux.bin
................\................\_xmsgs\xst.xmsgs
................\................\xst\dump.xst\conditional_adder_4bits.prj\ngx\notopt
................\................\...\........\...........................\...\opt
................\................\...\........\...........................\ngx
................\................\...\........\conditional_adder_4bits.prj
................\................\...\work\vlg10
................\................\...\....\vlg65
................\................\...\....\vlg66
................\................\work\adder_4bits
................\................\....\complement_adder
................\................\....\complement_adder_tb
................\................\....\conditional_adder_4bits
................\................\....\full_adder
................\................\....\glbl
................\................\....\mux
................\................\xst\dump.xst
................\................\...\projnav.tmp
................\................\...\work
............
................\................\adder_4bits.udo
................\................\adder_4bits.v
................\................\complement_adder.ise
................\................\complement_adder.ise_ISE_Backup
................\................\complement_adder.ntrc_log
................\................\complement_adder.restore
................\................\complement_adder_tb.fdo
................\................\complement_adder_tb.udo
................\................\complement_adder_tb.v
................\................\conditional_adder_4bits.cmd_log
................\................\conditional_adder_4bits.lso
................\................\conditional_adder_4bits.ngc
................\................\conditional_adder_4bits.ngr
................\................\conditional_adder_4bits.prj
................\................\conditional_adder_4bits.stx
................\................\conditional_adder_4bits.syr
................\................\conditional_adder_4bits.v
................\................\conditional_adder_4bits.xst
................\................\conditional_adder_4bits_summary.html
................\................\mux.v
................\................\transcript
................\................\vsim.wlf
................\................\work\adder_4bits\verilog.asm
................\................\....\...........\_primary.dat
................\................\....\...........\_primary.vhd
................\................\....\complement_adder\verilog.asm
................\................\....\................\_primary.dat
................\................\....\................\_primary.vhd
................\................\....\................_tb\verilog.asm
................\................\....\...................\_primary.dat
................\................\....\...................\_primary.vhd
................\................\....\..nditional_adder_4bits\verilog.asm
................\................\....\.......................\_primary.dat
................\................\....\.......................\_primary.vhd
................\................\....\full_adder\verilog.asm
................\................\....\..........\_primary.dat
................\................\....\..........\_primary.vhd
................\................\....\glbl\verilog.asm
................\................\....\....\_primary.dat
................\................\....\....\_primary.vhd
................\................\....\mux\verilog.asm
................\................\....\...\_primary.dat
................\................\....\...\_primary.vhd
................\................\....\_info
................\................\xst\dump.xst\conditional_adder_4bits.prj\ntrc.scr
................\................\...\work\hdllib.ref
................\................\...\....\vlg10\conditional__adder__4bits.bin
................\................\...\....\...65\adder__4bits.bin
................\................\...\....\....6\mux.bin
................\................\_xmsgs\xst.xmsgs
................\................\xst\dump.xst\conditional_adder_4bits.prj\ngx\notopt
................\................\...\........\...........................\...\opt
................\................\...\........\...........................\ngx
................\................\...\........\conditional_adder_4bits.prj
................\................\...\work\vlg10
................\................\...\....\vlg65
................\................\...\....\vlg66
................\................\work\adder_4bits
................\................\....\complement_adder
................\................\....\complement_adder_tb
................\................\....\conditional_adder_4bits
................\................\....\full_adder
................\................\....\glbl
................\................\....\mux
................\................\xst\dump.xst
................\................\...\projnav.tmp
................\................\...\work
............