资源列表
[VHDL编程] add
说明:一个用quartus原理图输入的全加器,(A full adder with quartus schematic input,)<zhangning194 > 在 2024-11-16 上传 | 大小:1kb | 下载:0
[VHDL编程] uart
说明:实现与电脑端串行数据发送与接收,波特率为9600(Realize serial data sending and receiving with the computer terminal)<hurricanhup > 在 2024-11-16 上传 | 大小:1kb | 下载:0
[VHDL编程] bist 2017 paper
说明:A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudora<Maddy619 > 在 2024-11-16 上传 | 大小:1.5mb | 下载:0
[VHDL编程] tengkan-V2.2
说明:Calculation crosshairs diffraction image at different distances, Channelized receiver based on multi-phase structure, Verification is available.<manjaofienen > 在 2024-11-16 上传 | 大小:148kb | 下载:0
[VHDL编程] basic_uart
说明:basic code for UART receiver and transmeter<Ravin48 > 在 2024-11-16 上传 | 大小:3kb | 下载:0
[VHDL编程] RS232_verilog1
说明:RS232通信协议verilog程序。经过调试可以使用(RS232 communication protocol Verilog program. After debugging can be used)<你好PSL > 在 2024-11-16 上传 | 大小:6.38mb | 下载:0