资源列表
[VHDL编程] Universal-Register
说明:Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements.<jgc> 在 2024-10-11 上传 | 大小:1024 | 下载:0
[VHDL编程] Octal-D-Type-Register
说明:Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements.<jgc> 在 2024-10-11 上传 | 大小:1024 | 下载:0
[VHDL编程] rom_con_aa
说明:VERILOG 多线程控制程序,实现状态机控制ad采集-VERILOG multi-threaded control program, to achieve a state machine control ad acquisition<张彬> 在 2024-10-11 上传 | 大小:1024 | 下载:0