资源列表
[VHDL编程] Function_clock_generate
说明:基于FPGA实现的实时闹钟,在DE2—115开发板上通过验证,实现报时,定时,时间调整等功能-Based on verified DE2-115 development board FPGA to achieve real-time alarm, timekeeping, timing, time adjustment<小梦> 在 2025-02-01 上传 | 大小:2kb | 下载:0
[VHDL编程] ImageRotate
说明:verilog实现图像旋转,可终合,并带有Testbench-verilog image rotation, and can be a final, and with Testbench<郑蔚> 在 2025-02-01 上传 | 大小:2kb | 下载:1
[VHDL编程] Core_fifo_w
说明:FPGA写FIFO操作,然后把FIFO里的数据送到编码器里编码成PAL格式,输出-write a picture to the fifo odd and evea ,then it can be used to encode into the PAL to display<wanggui> 在 2025-02-01 上传 | 大小:2kb | 下载:0
[VHDL编程] ADC_16bit
说明:16位ADC的verilog源代码 16-bit Analogue-Digital Converter-16-bit ADC verilog source code 16-bit Analogue-Digital Converter<wangzhenliang> 在 2025-02-01 上传 | 大小:2kb | 下载:0
[VHDL编程] Sum_of_2_rand
说明:We produce two 5-bit random numbers and then adds them. The two random numbers are generated by pressing two different push-buttons on the lab board. The addition is controlled by a third button, button3. it can be im<宋臣> 在 2025-02-01 上传 | 大小:2kb | 下载:0
[VHDL编程] lcd_driver
说明:在1602液晶模块上显示字符串,其中第一行显示“Welcom to hx" 在第二行显示“www.mcuhx.com- in 1602 LCD module display on a string, including the first line shows "Welcom to hx" In the second row shows "www.mcuhx.com<xuyawang> 在 2025-02-01 上传 | 大小:2kb | 下载:0