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[VHDL编程] FPGA_statu-machine
说明:FPGA 编程中常用的状态机编写风格和代码。开发环境为ISE10.1.-FPGA programming state machines commonly used in writing style and code.Development environment for ISE10.1.<lijin> 在 2025-01-31 上传 | 大小:2kb | 下载:0
[VHDL编程] verilog_divdier
说明:veilog中的常用分频器,包括2分频 4分频 8分频等 开发环境为ise8.2-veilog commonly used in the dividers, including the 2 frequency divided by 4 divided by 8, such as development environment for ise8.2<lijin> 在 2025-01-31 上传 | 大小:2kb | 下载:0
[VHDL编程] GFverilog-hdl
说明:伽罗华域的乘法器的设计,使用有限域设计乘法器-Galois field multiplier design, the use of finite field multiplier design<许皓天> 在 2025-01-31 上传 | 大小:2kb | 下载:0