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[VHDL编程] FIFO_Buffer
说明:Verilog的FIFO源代码,可综合,并以运用到具体工程中-Verilog source code of the FIFO can be integrated and applied to specific projects<david> 在 2024-11-14 上传 | 大小:1kb | 下载:0
[VHDL编程] shift_reg_ps
说明:this VHDL program can get a 64bit paralel data and make a serial data with SCLK and WCLK.<Taher Aghazadeh> 在 2024-11-14 上传 | 大小:1kb | 下载:0
[VHDL编程] shift_reg_sp
说明:this VHDL Progran get a SCLK(seril CLock) and a WCLK(Word CLOCK) with a serial data line and return a 64nits Parallel data.<Taher Aghazadeh> 在 2024-11-14 上传 | 大小:1kb | 下载:0
[VHDL编程] SAMP_RATE
说明:this VHDL program can count and measure a time of high-level of a signal by a high-frequency refrence signal.<Taher Aghazadeh> 在 2024-11-14 上传 | 大小:1kb | 下载:0