资源列表
[VHDL编程] add_unsigned1
说明:Adding Unsigned Numbers. Introduction. Adding numbers in binary is pretty much the same as adding in base ten. In fact, you could argue that it s even easier<omid> 在 2025-03-04 上传 | 大小:54kb | 下载:0
[VHDL编程] LabVHDL_10-12
说明:fpga clock alarm time-fpga clock alarm time<fpga> 在 2025-03-04 上传 | 大小:1.41mb | 下载:0
[VHDL编程] codes
说明:verilog code for carry look ahead adder.<Mohd. Abdul Khadeer> 在 2025-03-04 上传 | 大小:1.92mb | 下载:0
[VHDL编程] eight-gated-lock
说明:智能八位门控密码锁 可以实现自行设计密码 密码正确 门控电路开启 密码错误 报警电路响起-Microcontroller-based eight-gated lock Can design their own password Gating circuit is opened the password is correct Sounded the alarm circuit password is wrong<陶陶> 在 2025-03-04 上传 | 大小:58kb | 下载:0
[VHDL编程] AES
说明:Pipelined Implementation of AES Encryption Based on FPGA<rivercreamss> 在 2025-03-04 上传 | 大小:85kb | 下载:0